Kona_ADV VLSI project report

Kona_ADV VLSI project report - Data memor y Reg file...

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Unformatted text preview: Data memor y Reg file Control unit ALU I nstr uction memor y Regfile PC we x-1 we x-2 we x Memor y operation Read from regist er file Execution Fetch Wr it e back Read HD.Unit F.mux| Execution F.Unit Fetch Wr it e back h a c b d o b c d o D1 D2 D3 D4 D5 1 c d o D1 D2 D3 D4 D5 1 4 c d o D1 D2 D3 D4 D5 1 4 c d o D1 D2 D3 D4 D5 1 4 R5=4 d o D1 D2 D3 D4 D5 1 3 1 R5=1 R4=3 d o D1 D2 D3 D4 D5 1 2 1 1 R5=1 R4=1 R3=2 D1 o D2 D3 D4 D5 1 1 1 1 1 R5=1 R4=1 R3=1 R2=1 R1=0 RETIMING TO CONVERT SINGLE CYCLE TO PIPELINED DATAPATH Pratibha kona I ntroduction: Retiming is used to minimize the cycle time or area of synchronous circuits by changing the position of the registers [1]. Cycle time in any circuit is more than or equal to the maximum critical path delay of the combinational logic in synchronous circuits. By placing the registers in proper location this critical path delay can be reduced. We can use this methodology to convert a single cycle datapath into pipelined datapath. A pipelined dapapath has hazard conditions. A problem with direct retiming here is, it does not change the functionality of the datapath. So we should take care to include (specify) the hazard detection hardware before retiming. I ncluding hazard detection and Forwarding in datapath: A datapath can be pipelined into a number of stages depending on the individual operations and the time they take to perform them. Following is the general procedure for including the hazard unit for n number of pipeline stages, n being 5 in the example I have taken here(for MIPS architecture). Take a single cycle M IPS datapath. In this datapath we can see that , it can be divided into 5 pipeline stages as there are 5 fundamental units that carry out different functions in the datapath. If we assume a pipelined datapath with above individual blocks as different stages, we can see the possibility of the data hazards, when the destination of one instruction is going to be used in next few instructions. So these conditions are to be checked and proper hardware should be added to deal with the hazards.[2] RETIMING TO CONVERT SINGLE CYCLE TO PIPELINED DATAPATH Pratibha kona Conditions for hazards:...
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Kona_ADV VLSI project report - Data memor y Reg file...

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