lec3_verification

lec3_verification - ELEC 7770 ELEC Advanced VLSI Design...

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Unformatted text preview: ELEC 7770 ELEC Advanced VLSI Design Spring 2008 Verification Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 [email protected] http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr10/course.html Spring 2010, Jan 15 . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 1 VLSI Realization Process VLSI Customer’s need Design Determine requirements Write specifications Design synthesis and Verification Test development Fabrication Manufacture Manufacturing test Chips to customer Spring 2010, Jan 15 . . ELEC 7770: Advanced VLSI Design (Agrawal) 2 Origin of “Debugging” Origin Thomas Edison wrote in a letter in 1878: “It has been just so in all of my inventions. The first step is an intuition, and comes with a burst, then difficulties arise—this thing gives out and [it is] then that “Bugs” — as such little faults and difficulties are called — show themselves and months of intense watching, study and labor are requisite before commercial success or failure is certainly reached.” An interesting example of “debugging” was in 1945 when a computer failure was traced down to a moth that was caught in a relay between contacts (Figure 3-1). D. Gizopoulos (Editor), Advances in Electronic Testing: Challenges and Methodologies, Springer, 2006, Chapter 3, “Silicon Debug,” by D. Josephson and B. Gottlieb. Spring 2010, Jan 15 . . ELEC 7770: Advanced VLSI Design (Agrawal) 3 Verification and Testing Verification Specification Hardware design Manufacturing Verification 50-70% cost Spring 2010, Jan 15 . . Testing Silicon 30-50% cost ELEC 7770: Advanced VLSI Design (Agrawal) 4 Definitions Definitions Verification: Predictive analysis to ensure that the Verification: synthesized design, when manufactured, will perform the given I/O function. perform Alternative Definition: Verification is a process used Alternative to demonstrate the functional correctness of a design. design. Spring 2010, Jan 15 . . ELEC 7770: Advanced VLSI Design (Agrawal) 5 What is Being Verified? What Given a set of specification, Does the design do what was specified? RTL coding Specification Interpretation Verification J. Bergeron, Writing Testbenches: Functional Verification Of HDL Models, Springer, 2000. Spring 2010, Jan 15 . . ELEC 7770: Advanced VLSI Design (Agrawal) 6 Avoiding Interpretation Error Avoiding Use redundancy Specification n etatio r Interp Interp retati on Spring 2010, Jan 15 . . RTL coding Verification ELEC 7770: Advanced VLSI Design (Agrawal) 7 Methods of Verification Methods Simulation: Verify input-output behavior for Simulation: selected cases. selected Formal verification: Exhaustively verify inputoutput behavior: Equivalence checking Model checking Symbolic simulation Spring 2010, Jan 15 . . ELEC 7770: Advanced VLSI Design (Agrawal) 8 Equivalence Checking Equivalence Logic equivalence: Two circuits implement Logic identical Boolean function. identical Logic and temporal equivalence: Two finite state Logic machines have identical input-output behavior (machine equivalence). (machine Topological equivalence: Two netlists are Topological identical (graph isomorphism). identical Reference: S.-Y. Hwang and K.-T. Cheng, Reference: Formal Equivalence Checking and Design Debugging, Springer, 1998. Debugging Spring 2010, Jan 15 . . ELEC 7770: Advanced VLSI Design (Agrawal) 9 Compare Two Circuits Compare a a c f b Spring 2010, Jan 15 . . c b f Graphs isomorphic? Boolean functions identical? Timing behaviors identical? ELEC 7770: Advanced VLSI Design (Agrawal) 10 Model Checking Model Construct an abstract model of the system, usually Construct in the form of a finite-state machine (FSM). in Analytically prove that the model does not violate Analytically the properties (assertions) of original specification. the Reference: E. M. Clarke, Jr., O. Grumberg, and D. Reference: A. Peled, Model Checking, MIT Press, 1999. Model Specification RTL coding RTL Assertions Interpretation Spring 2010, Jan 15 . . Model checking ELEC 7770: Advanced VLSI Design (Agrawal) 11 Symbolic Simulation Symbolic Simulation with algebraic symbols rather than Simulation numerical values. numerical Self-consistency: A complex (more advanced) Self-consistency: design produces the same result as a much simpler (and previously verified) design. simpler Reference: R. B. Jones, Symbolic Simulation Reference: Methods for Industrial Formal Verification, Methods Springer, 2002. Springer, Spring 2010, Jan 15 . . ELEC 7770: Advanced VLSI Design (Agrawal) 12 Simulation: Testbench Simulation: Testbench (HDL) Design under verification (HDL) Spring 2010, Jan 15 . . ELEC 7770: Advanced VLSI Design (Agrawal) 13 Testbench Testbench HDL code: Generates stimuli Checks output responses Approaches: Blackbox Whitebox Greybox Metrics (unreliable): Statement coverage Path coverage Expression or branch coverage Spring 2010, Jan 15 . . ELEC 7770: Advanced VLSI Design (Agrawal) 14 Equivalence Checking Equivalence Definition: Establishing that two circuits are Definition: functionally equivalent. functionally Applications: Verify that a design is identical to specification. Verify that synthesis did not change the function. Verify that corrections made to a design did not Verify create new errors. create Spring 2010, Jan 15 . . ELEC 7770: Advanced VLSI Design (Agrawal) 15 Compare Two Circuits Compare a a c f b c b Are graphs isomorphic? Else, are Boolean functions identical? Then, are timing behaviors identical? Spring 2010, Jan 15 . . f ELEC 7770: Advanced VLSI Design (Agrawal) Yes Yes Yes 16 ATPG Approach (Miter) ATPG Circuit 1 (Verified design) Circuit 2 (Sythesized or modified design) stuck-at-0 stuck-at-0 Redundancy of a stuck-at-0 fault, checked by ATPG, establishes equivalence of the corresponding output pair. If the fault is detectable, its tests are used to diagnose the differences. Spring 2010, Jan 15 . . ELEC 7770: Advanced VLSI Design (Agrawal) 17 Difficulties with Miter Difficulties ATPG is NP-complete. When circuits are equivalent, proving When redundancy of faults is computationally expensive. expensive. When circuits are different, test vectors are When quickly found, but diagnosis is difficult. quickly Spring 2010, Jan 15 . . ELEC 7770: Advanced VLSI Design (Agrawal) 18 A Heuristic Approach Heuristic Derive V1, test vectors for all faults in C1. Derive V2, test vectors for all faults in C2. If the combined set, V1+V2, produces the same If outputs from the two circuits, then they are probably equivalent. probably Reference: V. D. Agrawal, “Choice of Tests for Reference: Logic Verification and Equivalence Checking and the Use of Fault Simulation,” Proc. 13th Proc. International Conf. VLSI Design, January 2000, International January pp. 306-311. pp. Spring 2010, Jan 15 . . ELEC 7770: Advanced VLSI Design (Agrawal) 19 Example Circuit C1 Example x1 C1 x2 x3 x4 Tests 1 C1 = x1 x3 x4 + x2 x3 + x2 x4 x1 1 1 x3 1 1 1 x2 1 1 Spring 2010, Jan 15 . . ELEC 7770: Advanced VLSI Design (Agrawal) x4 20 Example Circuit C2 Example x1 x2 C2 x3 x4 Tests 1 C2 = x1 x3 x4 + x2 x3 + x2 x4 x1 1 1 x3 1 1 1 x2 1 1 Spring 2010, Jan 15 . . ELEC 7770: Advanced VLSI Design (Agrawal) x4 21 C1 ≡ C2 Tests 1 x1 1 1 x3 1 Tests 1 1 1 1 x2 x1 1 1 x3 1 1 1 1 1 1 x4 x4 C1 Spring 2010, Jan 15 . . x2 C2 ELEC 7770: Advanced VLSI Design (Agrawal) 22 C2’: Erroneous Implementation of C2 C2’: x1 x2 C2’ x3 x4 Tests x3 C2’ = x1 x2 x3 x4 + x2 x3 + x2 x4 C2 = x1 x3 x4 + x2 x3 + x2 x4 1 x1 1 1 1 1 1 1 Spring 2010, Jan 15 . . ELEC 7770: Advanced VLSI Design (Agrawal) x4 x2 minterm deleted 23 Incorrect Result: C1 ≡ C2’ C2’ C1 = x1 x3 x4 + x2 x3 + x2 x4 Tests 1 x1 x3 1 1 C2’ = x1 x2 x3 x4 + x2 x3 + x2 x4 1 Tests 1 1 1 x3 1 x2 x1 1 1 1 1 1 1 1 x4 Spring 2010, Jan 15 . . x4 ELEC 7770: Advanced VLSI Design (Agrawal) x2 minterm deleted 24 s-a-0 Additional Safeguard Additional C1 (Verified design) 0 s-a-1 C2 (Sythesized or modified design) Simulate V1+V2 for equivalence: Output always 0 No single fault on PI’s detected Still not perfect Spring 2010, Jan 15 . . ELEC 7770: Advanced VLSI Design (Agrawal) 25 Probabilistic Equivalence Probabilistic Consider two Boolean functions F and G of the same set Consider of input variables {X1, . . . , Xn}. of Let f = Prob(F=1), g = Prob(G=1), xi = Prob(Xi=1) For any arbitrarily given values of xi, if f = g, then F and G For are equivalent with probability 1. are References: J. Jain, J. Bittner, D. S. Fussell and J. A. Abraham, “Probabilistic J. Verification of Boolean Functions,” Formal Methods in System Design, vol. 1, pp 63-117, 1992. Design, V. D. Agrawal and D. Lee, “Characteristic Polynomial Method for V. Verification and Test of Combinational Circuits,” Proc. 9th Verification International Conf. VLSI Design, January 1996, pp. 341-342. International Spring 2010, Jan 15 . . ELEC 7770: Advanced VLSI Design (Agrawal) 26 Simplest Example Simplest F = X1.X2, X1.X2, G = X1+X2, X1+X2, f = x1 x2 x1 g = (1 – x1)(1 – x2) (1 = 1 – x1 – x2 + x1 x2 x1 Input probabilities, x1 and x2, are randomly Input taken from {0.0, 1.0} taken We make a wrong decision if f = g, i.e., x1x2 = 1 – x1 – x2 + x1 x2 or x1 + x2 = 1 Spring 2010, Jan 15 . . ELEC 7770: Advanced VLSI Design (Agrawal) 27 Probability of Wrong Decision Probability x2 Randomly selected point (x1,x2) 1.0 x1 + x2 = 1 0 1.0 x1 Probability of wrong decision = Random point falls on line {x1 + x2 = 1} = (area of line)/(area of unit square) =0 Spring 2010, Jan 15 . . ELEC 7770: Advanced VLSI Design (Agrawal) 28 Calculation of Signal Probability Calculation Exact calculation Exponential complexity. Affected by roundoff errors. Alternative: Monte Carlo method Randomly select input probabilities Generate random input vectors Simulate circuits F and G IIf outputs have a mismatch, circuits are not f equivalent. equivalent. Else, stop after “sufficiently” large number of vectors Else, (open problem). (open Spring 2010, Jan 15 . . ELEC 7770: Advanced VLSI Design (Agrawal) 29 References on Signal Probability References S. C. Seth and V. D. Agrawal, “A New Model for S. Computation of Probabilistic Testability in Combinational Circuits,” INTEGRATION, The VLSI Journal, vol. 7, pp. 49-75, 1989. VLSI V. D. Agrawal and D. Lee and H. Woźniakowski, niakowski, “Numerical Computation of Characteristic Polynomials of Boolean Functions and its Applications,” Numerical Algorithms, vol. 17, pp. Numerical vol. 261-278, 1998. Spring 2010, Jan 15 . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 30 More on Equivalence Checking More Don’t cares Sequential circuits Time-frame expansion Initial state Design debugging (diagnosis) Reference: S.-Y. Hwang and K.-T. Cheng, Reference: Formal Equivalence Checking and Design Debugging, Springer, 1998. Debugging Spring 2010, Jan 15 . . ELEC 7770: Advanced VLSI Design (Agrawal) 31 Methods of Equivalence Checking Methods Satisfiability algorithms ATPG methods Binary decision diagrams (BDD) Spring 2010, Jan 15 . . ELEC 7770: Advanced VLSI Design (Agrawal) 32 Shannon’s Expansion Theorem Shannon’s C. E. Shannon, “A Symbolic Analysis of Relay and C. Switching Circuits,” Trans. AIEE, vol. 57, pp. 713-723, Trans. vol. 1938. 1938. Consider: Boolean variables, X1, X2, . . . , Xn Boolean function, F(X1, X2, . . . , Xn) Then F = Xi F(Xi=1) + Xi’ F(Xi=0) Where Xi’ is complement of Xi Cofactors, F(Xi=j) = F(X1, X2, . . , Xi=j, . . , Xn), j = 0 or 1 Spring 2010, Jan 15 . . ELEC 7770: Advanced VLSI Design (Agrawal) 33 Claude E. Shannon (1916-2001) Claude http://www.kugelbahn.ch/sesam_e.htm Spring 2010, Jan 15 . . ELEC 7770: Advanced VLSI Design (Agrawal) 34 Shannon’s Legacy Shannon’s A Symbolic Analysis of Relay and Switching Circuits, Master’s Thesis, MIT, 1940. Perhaps the most influential Master’s MIT, master’s thesis of the 20th century. master’s An Algebra for Theoretical Genetics, PhD Thesis, MIT, MIT, 1940. 1940. Founded the field of Information Theory. C. E. Shannon and W. Weaver, The Mathematical C. Theory of Communication, University of Illinois Press, 1949. A “must read.” “must Spring 2010, Jan 15 . . ELEC 7770: Advanced VLSI Design (Agrawal) 35 Theorem Theorem (1) F = Xi F(Xi = 1) + Xi’ F(Xi = 0) ∀ i = 1,2,3, . . . n (2) F = (Xi + F(Xi = 0)) (Xi’ + F(Xi = 1)) ∀ i = 1,2,3, . . . n F(Xi = 0) Xi F(Xi = 1) 0 1 F Spring 2010, Jan 15 . . ELEC 7770: Advanced VLSI Design (Agrawal) 36 Expansion About Two Inputs Expansion F = XiXj F(Xi = 1, Xj = 1) + XiXj’ F(Xi = 1, Xj = 0) XiXj’ + Xi’Xj F(Xi = 0, Xj = 1) + Xi’Xj’ F(Xi = 0, Xj = 0) In general, a Boolean function can be expanded In about any number of input variables. about Expansion about k variables will have 2k terms. Spring 2010, Jan 15 . . ELEC 7770: Advanced VLSI Design (Agrawal) 37 Binary Decision Tree Binary a a c b 0 c Graph representation of a Boolean function. 1 0 f b 0 1 0 1 0 0 0 b c 1 1 c 1 0 0 0 c 1 0 1 1 1 1 Leaf nodes Spring 2010, Jan 15 . . ELEC 7770: Advanced VLSI Design (Agrawal) 38 Binary Decision Diagrams Binary Binary decision diagram (BDD) is a graph representation Binary of a Boolean function, directly derivable from Shannon’s expansion. expansion. References: C. Y. Lee, “Representation of Switching Circuits by Binary C. Decision Diagrams,” Bell Syst. Tech J., vol. 38, pp. 985-999, Bell ., July 1959. July S. Akers, “Binary Decision Diagrams,” IEEE Trans. Computers, S. IEEE vol. C-27, no. 6, pp. 509-516, June 1978. vol. Ordered BDD (OBDD) and Reduced Order BDD Ordered (ROBDD). (ROBDD). Reference: R. E. Bryant, “Graph-Based Algorithms for Boolean Function R. Manipulation,” IEEE Trans. Computers, vol. C-35, no. 8, pp. 677IEEE 691, August 1986. Spring 2010, Jan 15 . . ELEC 7770: Advanced VLSI Design (Agrawal) 39 Binary Decision Diagram Binary BDD of an n-variable Boolean function is a tree: Root node is any input variable. All nodes in a level are labeled by the same input All variable. variable. Each node has two outgoing edges, labeled as 0 and Each 1 indicating the state of the node variable. indicating Leaf nodes carry fixed 0 and 1 labels. Levels from root to leaf nodes represent an ordering Levels of input variables. of If we trace a path from the root to any leaf, the label If of the leaf gives the value of the Boolean function when inputs are assigned the values from the path. when Spring 2010, Jan 15 . . ELEC 7770: Advanced VLSI Design (Agrawal) 40 Ordered Binary Decision Diagram (OBDD) (OBDD) a a c b 1 0 f b 0 1 0 b 0 0 0 a 1 0 c1 0 1 b 1 0c 10 c1 0c 1 0100111 0 0 c 1 Tree Spring 2010, Jan 15 . . b ELEC 7770: Advanced VLSI Design (Agrawal) 1 c 1 0 0 0 1 1 1 OBDD 41 OBDD With Different Input Ordering With a c b a b 0 c 1 Spring 2010, Jan 15 . . 0 0 0 b b 1 c 1 1 0 0 1 0 c 1 0 0 f 0 0 1 a 1 0 1 1 0 ELEC 7770: Advanced VLSI Design (Agrawal) 1 b 1 a 10 1 0101 42 Evaluating Function from OBDD Evaluating Start at leaf nodes and work toward the root – Start leaf node functions are 0 and 1. leaf Function at a node with variable x is f = x’.f(low) + x.f(high) x 0 low Spring 2010, Jan 15 . . 1 high ELEC 7770: Advanced VLSI Design (Agrawal) 43 Cannot Compare Two Circuits Cannot a a c f b 0 c 0 1 Spring 2010, Jan 15 . . 0 b a 1 0 0 c b 1 b 0 f 1 b 1 a 0 1 0 1 10 1 0101 c ELEC 7770: Advanced VLSI Design (Agrawal) 0 0 a 1 1 44 OBDD Graph Isomorphism OBDD Two OBDDs are isomorphic if there is one-to one mapping between the vertex sets with one respect to adjacency, labels and leaf values. respect Two isomorphic OBDDs represent the same Two function. function. Two identical circuits may not have identical Two OBDDs even when same variable ordering is used. used. Comparison is possible if: Same variable ordering is used. Any redundancies in graphs are removed. Spring 2010, Jan 15 . . ELEC 7770: Advanced VLSI Design (Agrawal) 45 Reduced Ordered BDD (ROBDD) Reduced Directed acyclic graph (DAG) (*). Directed (*) Contains just two leaf nodes labeled 0 and 1. Variables are indexed, 1, 2, . . . n, such that the Variables index of a node is greater than that of its child (*). (*) A node has exactly two child nodes, low and node high such that low ≠ high. high. Graph contains no pair of nodes such that Graph subgraphs rooted in them are isomorphic. subgraphs * Properties common to OBDD. Spring 2010, Jan 15 . . ELEC 7770: Advanced VLSI Design (Agrawal) 46 ROBDDs ROBDDs a a c f b 0 0 c 1 1 0 Spring 2010, Jan 15 . . c b c b 0 f 0 a Isomorphic graphs 1 b 1 0 1 1 ELEC 7770: Advanced VLSI Design (Agrawal) 0 0 a 1 1 47 Reduction: OBDD to ROBDD OBDD a c b a b 0 0 c 1 Spring 2010, Jan 15 . . 1 c 1 0 0 0 b b 0 1 0 a 1 0 0 f 1 1 1 0 0 1 0 ELEC 7770: Advanced VLSI Design (Agrawal) 1 c 1 b 0 c 1 1 0 1 48 Properties of ROBDD Properties Unique for given variable ordering – graph isomorphism Unique verifies logic equivalence. verifies Size (number of nodes) changes with variable ordering – Size worst-case size is exponential (e.g., integer multiplier). worst-case Other applications: logic synthesis, testing. For algorithms to derive ROBDD, see R. E. Bryant, “Graph-Based Algorithms for Boolean Function R. Manipulation,” IEEE Trans. Computers, vol. C-35, no. 8, pp. 677IEEE 691, August 1986. G. De Micheli, Synthesis and Optimization of Digital Circuits, G. Synthesis New York: McGraw-Hill, 1994. New S. Devadas, A. Ghosh, and K. Keutzer, Logic Synthesis, New S. Logic New York: McGraw-Hill, 1994. York: Spring 2010, Jan 15 . . ELEC 7770: Advanced VLSI Design (Agrawal) 49 ...
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This note was uploaded on 09/16/2011 for the course ELEC 7770 taught by Professor Agrawal,v during the Spring '08 term at Auburn University.

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