lec4_timing

lec4_timing - ELEC 7770 ELEC Advanced VLSI Design Spring...

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Unformatted text preview: ELEC 7770 ELEC Advanced VLSI Design Spring 2010 Timing Simulation and STA Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University, Auburn, AL 36849 vagrawal@eng.auburn.edu http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr10/course.html Spring 10, Jan 25 . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 1 Digital Circuit Timing Digital Input Signal changes Synchronized With clock Outputs Comb. logic Spring 10, Jan 25 . . Transient region Inputs Output Observation instant ELEC 7770: Advanced VLSI Design (Agrawal) time Clock period 2 Timing Analysis and Optimization Timing Timing analysis Dynamic analysis: Simulation. Static timing analysis (STA): Vector-less topological analysis of Static circuit. circuit. Timing optimization Performance Clock design Other forms of design optimization Chip area Testability Power Spring 10, Jan 25 . . ELEC 7770: Advanced VLSI Design (Agrawal) 3 Circuit Delays Circuit Switching or inertial delay is the interval between input Switching change and output change of a gate: change Depends on input capacitance, device (transistor) Depends characteristics and output capacitance of gate. characteristics Also depends on input rise or fall times and states of other Also inputs (second-order effects). inputs Approximation: fixed rise and fall delays (or min-max delay Approximation: range, or single fixed delay) for gate output. range, Propagation or interconnect delay is the time a transition Propagation takes to travel between gates: takes Depends on transmission line effects (distributed R, L, C Depends Spring 10, Jan 25 . . parameters, length and loading) of routing paths. parameters, Approximation: modeled as lumped delays for gate inputs. ELEC 7770: Advanced VLSI Design (Agrawal) 4 Spice Spice Circuit/device level analysis Circuit modeled as network of transistors, capacitors, Circuit resistors and voltage/current sources. resistors Node current equations using Kirchhoff’s current law. Analysis is accurate but expensive Used to characterize parts of a larger circuit. Original references: L. W. Nagel and D. O. Pederson, “SPICE – Simulation L. Program With Integrated Circuit Emphasis,” Memo ERLProgram M382, EECS Dept., University of California, Berkeley, Apr. M382, 1973. 1973. L. W. Nagel, SPICE 2, A Computer program to Simulate L. Semiconductor Circuits, PhD Dissertation, University of Semiconductor PhD California, Berkeley, May 1975. California, Spring 10, Jan 25 . . ELEC 7770: Advanced VLSI Design (Agrawal) 5 Logic Model of MOS Circuit Logic pMOS FETs VDD a a Ca c Cc b Cb nMOS FETs Cd Ca , Cb , Cc and Cd are node capacitances Spring 10, Jan 25 . . b Da Db c Dc Da and Db are interconnect or propagation delays Dc is inertial delay of gate ELEC 7770: Advanced VLSI Design (Agrawal) 6 Spice Characterization Spice Input data pattern Delay (ps) Dynamic energy (pJ) a=b=0→1 69 1.55 a = 1, b = 0 → 1 62 1.67 a = 0 → 1, b = 1 50 1.72 a=b=1→0 35 1.82 a = 1, b = 1 → 0 76 1.39 a = 1 → 0, b = 1 57 1.94 Spring 10, Jan 25 . . ELEC 7770: Advanced VLSI Design (Agrawal) 7 Spice Characterization (Cont.) Spice Input data pattern a=b=0 5.05 a = 0, b = 1 13.1 a = 1, b = 0 5.10 a=b=1 Spring 10, Jan 25 . . Static power (pW) 28.5 ELEC 7770: Advanced VLSI Design (Agrawal) 8 Complex Gates: Switch-Level Partitions Complex Circuit partitioned into channel-connected components for Spice Circuit channel-connected characterization. characterization. Reference: R. E. Bryant, “A Switch-Level Model and Simulator for Reference: MOS Digital Systems,” IEEE Trans. Computers, vol. C-33, no. 2, pp. IEEE vol. 160-177, Feb. 1984. 160-177, Internal switching nodes not seen by logic simulator Spring 10, Jan 25 . . G2 G1 G3 ELEC 7770: Advanced VLSI Design (Agrawal) 9 Interconnect Delay: Elmore Delay Model Interconnect W. Elmore, “The Transient Response of Damped Linear Networks with W. Particular Regard to Wideband Amplifiers,” J. Appl. Phys., vol. 19, J. ., no.1, pp. 55-63, Jan. 1948. no.1, 2 R2 s R1 C2 1 4 R4 C1 Shared resistance: C4 R3 3 R5 C3 R45 = R1 + R3 R15 = R1 R34 = R1 + R3 Spring 10, Jan 25 . . 5 C5 ELEC 7770: Advanced VLSI Design (Agrawal) 10 Elmore Delay Formula Elmore N Delay at node k = 0.69 Σ Cj × Rjk j =1 where N = number of capacitive nodes in the network Example: Delay at node 5 = 0.69 [ R1 C1 + R1 C2 + (R1+R3)C3 + (R1+R3)C4 (R1+R3+R5)C5 ] Spring 10, Jan 25 . . ELEC 7770: Advanced VLSI Design (Agrawal) 11 Event Propagation Delays Event Single lumped inertial delay modeled for each gate PI transitions assumed to occur without time skew Path P1 1 0 13 P2 0 0 Spring 10, Jan 25 . . 2 1 3 2 246 P3 5 ELEC 7770: Advanced VLSI Design (Agrawal) 12 Circuit Outputs Circuit Each path can potentially produce one signal Each transition at the output. transition The location of an output transition in time is The determined by the delay of the path. determined Clock period Final value Initial value Slow transitions Fast transitions time Initial value Spring 10, Jan 25 . . Final value ELEC 7770: Advanced VLSI Design (Agrawal) 13 Delay and Discrete-Event Simulation Delay Inputs (NAND gate) Transient region a b c (CMOS) Logic simulation c (zero delay) c (unit delay) X c (multiple delay) Unknown (X) c (minmax delay) 0 Spring 10, Jan 25 . . 5 ELEC 7770: Advanced VLSI Design (Agrawal) rise=5, fall=5 min =2, max =5 Time units 14 Event-Driven Simulation Event-Driven (Example) 2 e =1 g =1 2 2 d=0 4 b =1 f =0 Time stack a =1 c =1→0 Scheduled events t=0 1 2 3 4 5 6 7 8 Activity list c=0 d, e d = 1, e = 0 f, g g=0 f=1 g g=1 g 0 Spring 10, Jan 25 . . 4 8 Time, t ELEC 7770: Advanced VLSI Design (Agrawal) 15 Time Wheel (Circular Stack) Time Current time pointer max t=0 1 Event link-list 2 3 4 5 6 7 Spring 10, Jan 25 . . ELEC 7770: Advanced VLSI Design (Agrawal) 16 Timing Design and Delay Test Timing Timing simulation: Critical paths are identified by static (vector-less) Critical timing analysis tools like Primetime (Synopsys). Primetime Timing or circuit-level simulation using designergenerated functional vectors verifies the design. Layout optimization: Critical path data are used in Layout placement and routing. Delay parameter extraction, timing simulation and layout are repeated for iterative improvement. repeated Testing: Some form of at-speed test is necessary. Testing: Critical paths and all gate transition delays are tested. Spring 10, Jan 25 . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 17 Static Timing Analysis (STA) Static Finds maximum and minimum delays between Finds Flip-flops Combinational circuit Flip-flops Flip-flops all clocked flip-flops. all Spring 10, Jan 25 . . ELEC 7770: Advanced VLSI Design (Agrawal) 18 Early References Early T. I. Kirkpatrick and N. R. Clark, “PERT as an T. Aid to Logic Design,” IBM J. Res. Dev., vol. 10, IBM ., no. 2, pp. 135-141, March 1966. no. R. B. Hitchcock, Sr., “Timing Verification and the R. Timing Analysis Program,” Proc. 19th Design Proc. Automation Conf., 1982, pp. 594-604. Automation V. D. Agrawal, “Synchronous Path Analysis in V. MOS Circuit Simulator,” Proc. 19th Design Proc. Automation Conf., 1982, pp. 629-635. Automation Spring 10, Jan 25 . . ELEC 7770: Advanced VLSI Design (Agrawal) 19 Basic Ideas Basic Adopted from project management Frederick W. Taylor (1856-1915) Henry Gantt (1861-1919) PERT – Program Evaluation and Review PERT Technique Technique CPM – Critical Path Method Spring 10, Jan 25 . . ELEC 7770: Advanced VLSI Design (Agrawal) 20 A Gantt Chart in Microsoft Excel Gantt Spring 10, Jan 25 . . ELEC 7770: Advanced VLSI Design (Agrawal) 21 Using a Gantt Chart Using Track progress of subtasks and project. Assess resource needs as a function of time. Spring 10, Jan 25 . . ELEC 7770: Advanced VLSI Design (Agrawal) 22 Pert Chart Pert Spring 10, Jan 25 . . ELEC 7770: Advanced VLSI Design (Agrawal) 23 Example: Thesis Research Example: Begin Defense done Analysis completed 4, 4, 4 2, 4, 6 weeks 2, 3, 4 4, 5, 6 Problem selected 3, 4, 5 minimum average maximum Spring 10, Jan 25 . . 2, 2, 2 Background study completed 5, 7, 9 Program and Experiment completed Thesis Draft done Thesis submitted 4, 4, 4 ELEC 7770: Advanced VLSI Design (Agrawal) 24 Critical Path Critical Begin Defense done Analysis completed 4, 4, 4 2, 4, 6 weeks 2, 3, 4 4, 5, 6 Problem selected 3, 4, 5 minimum average maximum Spring 10, Jan 25 . . 2, 2, 2 Background study completed 5, 7, 9 Program and Experiment completed Thesis Draft done Thesis submitted 4, 4, 4 Critical path is path of maximum average delay (24 weeks). ELEC 7770: Advanced VLSI Design (Agrawal) 25 A Basic Timing Analysis Algorithm Basic Combinational logic. Circuit represented as an acyclic directed graph Circuit (DAG). (DAG). Gates characterized by delays. Spring 10, Jan 25 . . ELEC 7770: Advanced VLSI Design (Agrawal) 26 Example Example Levelize graph. Initialize arrival times at primary inputs. 0 0 A 1 0 0 B 3 0 0 C 1 0 0 evel 0 H 3 E 1 G 2 F 1 D 2 1 Spring 10, Jan 25 . . J 1 2 3 ELEC 7770: Advanced VLSI Design (Agrawal) 4 5 27 Example (Cont.) Example Determine output arrival time when all input arrival times are known. 0 A1 H 10 1 0 3 0 0 B3 3 0 0 C1 1 0 0 evel 0 D2 2 1 Spring 10, Jan 25 . . E4 1 G7 2 J8 1 F5 1 2 3 ELEC 7770: Advanced VLSI Design (Agrawal) 4 5 28 Example (Cont.) Example Trace critical path from the output with longest arrival time. 0 A1 H 10 1 0 3 0 0 B3 3 0 0 C1 1 0 0 evel 0 D2 2 1 Spring 10, Jan 25 . . E4 1 G7 2 J8 1 F5 1 2 3 ELEC 7770: Advanced VLSI Design (Agrawal) 4 5 29 Finding Earliest and Longest Times Finding 0 0 A 1,1 1 0 0 B 3,3 3 0 0 C 1,1 1 0 0 D 2,2 2 evel 0 1 Spring 10, Jan 25 . . H 4,10 3 E 2,4 1 G 4,7 2 J 4,8 1 F 3,5 1 2 3 ELEC 7770: Advanced VLSI Design (Agrawal) 4 5 30 Shortest and Longest Paths Shortest 0 0 A 1,1 1 0 0 B 3,3 3 0 0 C 1,1 1 0 0 D 2,2 2 Spring 10, Jan 25 . . H 4,10 3 E 2,4 1 G 4,7 2 F 3,5 1 ELEC 7770: Advanced VLSI Design (Agrawal) J 4,8 1 31 Characteristics of STA Characteristics Linear time analysis, Complexity is O(n), n is Linear number of gates and interconnects. number Variations: Find k longest paths: S. Kundu, “An Incremental Algorithm for Identification of S. Longest (Shortest) Paths,” Integration, the VLSI Journal, vol. Longest Integration, 17, no. 1, pp. 25-35, August 1994. 17, Find worst-case delays from an input to all outputs. Linear programming methods. Spring 10, Jan 25 . . ELEC 7770: Advanced VLSI Design (Agrawal) 32 Algorithms for Directed Acyclic Graphs (DAG) (DAG) Graph size: n = |V| + |E|, for |V| vertices and |E| Graph edges. edges. Levelization: O(n) (linear-time) algorithm finds Levelization: the maximum (or minimum) depth. the Path counting: O(n2) algorithm. Number of paths algorithm. can be exponential in n. can Finding all paths: Exponential-time algorithm. Shortest (or longest) path between two nodes: Dijkstra’s algorithm: O(n2) Bellman-Ford algorithm: O(n3) Spring 10, Jan 25 . . ELEC 7770: Advanced VLSI Design (Agrawal) 33 References References Delay modeling, simulation and testing: M. L. Bushnell and V. D. Agrawal, Essentials of Electronic M. Testing for Digital, Memory and Mixed-Signal VLSI Circuits, Testing Springer, 2000. Springer, Analysis and Design: G. De Micheli, Synthesis and Optimization of Digital Circuits, G. Synthesis McGraw-Hill, 1994. McGraw-Hill, N. Maheshwari and S. S. Sapatnekar, Timing Analysis and N. Optimization of Sequential Circuits, Springer, 1999. Optimization PrimeTime (Static timing analysis tool): H. Bhatnagar, Advanced ASIC Chip Synthesis, Second Edition, H. Advanced Springer, 2002 Springer, Spring 10, Jan 25 . . ELEC 7770: Advanced VLSI Design (Agrawal) 34 ...
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