lec5_timing_verification

lec5_timing_verification - ELEC 7770 Advanced VLSI Design...

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Unformatted text preview: ELEC 7770 Advanced VLSI Design Spring 2010 Timing Verification and Optimization Timing Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University, Auburn, AL 36849 [email protected] http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr10/course.html Spring 2010, Feb 1 Spring ELEC 7770: Advanced VLSI Design (Agrawal) 1 Proof of Correctness Static timing analysis proves the timing Static correctness. That is, the circuit is guaranteed to work at the clock rate determined by the critical path. path. But the circuit may also work correctly at faster But speeds. speeds. Because the critical path identified by STA Because (static timing analysis) may be a “false path”. (static STA overestimates the delay of the circuit. Spring 2010, Feb 1 Spring ELEC 7770: Advanced VLSI Design (Agrawal) 2 False and True Paths A ffalse path cannot propagate an event and hence alse cannot affect the timing of the circuit. False paths are dynamically unsensitizable. dynamically Dynamically sensitizable path (true path): All off-path Dynamically inputs must settle down to their non-controlling values when the event propagates through the path. when a b c 1 0 d1 True path of length 3 e 2 1 1 y f 1 1 3 0 Spring 2010, Feb 1 Spring ELEC 7770: Advanced VLSI Design (Agrawal) 1 4 True path of length 4 z 3 Static Sensitization of Path Static sensitization of path: All off-path inputs can be Static simultaneously set to their non-controlling values. simultaneously Longest path in the following example is statically Longest unsensitizable. Such paths are often referred to, though not correctly (why?), as false paths. not as True path of length 3 a d1 1 e 2 1 1 b 0 Spring 2010, Feb 1 Spring y 1 3 1 1 z f 1 ELEC 7770: Advanced VLSI Design (Agrawal) False path of length 4 4 An Example Statically unsensitizable (false) path. P. C. McGeer and R. K. Brayton, Integrating P. Functional and Temporal Domains in Logic Design, Springer, 1991. Design a False path of delay 3 e 1 0 1 d b c 1 1 1 0 g f 0 Spring 2010, Feb 1 Spring ELEC 7770: Advanced VLSI Design (Agrawal) 5 Example (Cont.) Another statically unsensitizable false path. P. C. McGeer and R. K. Brayton, Integrating P. Functional and Temporal Domains in Logic Design, Springer, 1991. Design a 1 Two false paths of delay 3 e 1 0 1 d b c 1 1 0 g f 0 Spring 2010, Feb 1 Spring ELEC 7770: Advanced VLSI Design (Agrawal) 6 Example (Cont.) Two paths are dynamically sensitizable and will affect the Two timing if both are together faulty. timing P. C. McGeer and R. K. Brayton, Integrating Functional P. and Temporal Domains in Logic Design, Springer, 1991. and a False paths of delay 3 e 1 23 1 d b c 1 1 g f 0 Spring 2010, Feb 1 Spring ELEC 7770: Advanced VLSI Design (Agrawal) 7 Static Sensitization Condition x y z Off-path inputs There must exist an input vector (PI) that satisfies the following conditions: ∂y/∂x = 1, ∂z/∂y = 1, . . . Where ∂y/∂x = y(x=1, PI) ⊕ y(x=0, PI) is Boolean difference Spring 2010, Feb 1 Spring ELEC 7770: Advanced VLSI Design (Agrawal) 8 An ATPG Method x y z Stuck-at-0 Path is false if this fault is redundant Spring 2010, Feb 1 Spring ELEC 7770: Advanced VLSI Design (Agrawal) 9 Optimism and Pessimism Statically Dynamically sensitizable sensitizable Paths paths (optimistic) Structural paths analyzed by STA (pessimistic) Spring 2010, Feb 1 Spring ELEC 7770: Advanced VLSI Design (Agrawal) 10 Theorem 1 Every statically sensitizable path is dynamically Every sensitizable. sensitizable. Proof: Since a vector exists to sensitize the path, Proof: if that vector does not specify the path input, then toggling the primary input at the origin of the path will propagate an event through the path. path. P. C. McGeer and R. K. Brayton, Integrating P. Functional and Temporal Domains in Logic Design, Springer, 1991, p. 35. Design Spring 2010, Feb 1 Spring ELEC 7770: Advanced VLSI Design (Agrawal) 11 Theorem 2 The longest path in a circuit is dynamically The sensitizable iff it is statically sensitizable. sensitizable Proof: Because this is the longest path, all offpath inputs will settle to their sensitizing values path at the inputs of any gate before the on-path event propagates through that gate. event P. C. McGeer and R. K. Brayton, Integrating P. Functional and Temporal Domains in Logic Design, Springer, 1991, p. 37. Design Spring 2010, Feb 1 Spring ELEC 7770: Advanced VLSI Design (Agrawal) 12 Proof of Theorem 2 Case 1: Static sensitization does not specify the Case value at the path origin. value Toggling the path origin will propagate an event Toggling through the path causing dynamic sensitization. through Example: 1 0 A 01 or 10 here will propagate through the path Spring 2010, Feb 1 Spring Statically sensitized path ELEC 7770: Advanced VLSI Design (Agrawal) 13 Proof of Theorem 2 (Cont.) Case 2: Static sensitization specifies the value at the path origin. Toggling the path origin will propagate an event through the path Toggling causing dynamic sensitization because the event on the longest path will see all gates sensitized through shorter paths. path Example: This event Shorter path sets this to 1 before the event arrives on the longest path 0 propagated through longest path 01 1 Apply 01 event here Spring 2010, Feb 1 Spring Statically sensitized path ELEC 7770: Advanced VLSI Design (Agrawal) 14 Proof of Theorem 2 (Cont.) Case 3: Longest path is statically unsensitizable. Toggling the path origin will not propagate any Toggling event through the path. Toggling other input only dynamically sensitizes shorter path. dynamically This event did Example: Shorter path sets this to 1 before the event arrives on the longest path 01 01 Apply 01 events Spring 2010, Feb 1 Spring not propagate through longest path 01 Statically unsensitizable path ELEC 7770: Advanced VLSI Design (Agrawal) 15 Speeding Up a Circuit 2 a 3 False path w a x 2 w u 2 2 v 2 y z u v x y z 0 1 2 3 4 5 6 7 time Spring 2010, Feb 1 Spring ELEC 7770: Advanced VLSI Design (Agrawal) 16 Speeding Up a Circuit 2 a 3 False path w a x 2 w u 2 2 v 2 y z u v x y z 0 1 2 3 4 5 6 7 time Spring 2010, Feb 1 Spring ELEC 7770: Advanced VLSI Design (Agrawal) 17 Speeding Up a Circuit Reducing the delay of a false path can increase circuit delay. 2 a 1 w a x 2 w u 2 2 v 2 y z u v x y z 0 1 2 3 4 5 6 7 time Spring 2010, Feb 1 Spring ELEC 7770: Advanced VLSI Design (Agrawal) 18 Speeding Up a Circuit 2 a 1 False path w a x 2 w u 2 2 v 2 y z u v x y z 0 1 2 3 4 5 6 7 time Spring 2010, Feb 1 Spring ELEC 7770: Advanced VLSI Design (Agrawal) 19 A Delay Optimization Algorithm REDUCE_DELAY (Circuit graph (V, E), ε) REDUCE_DELAY Repeat { Compute critical paths and critical delay Δ Compute Set output data ready time to Δ Set Compute slacks U = vertex subset with slack < ε vertex W = select vertices in U Apply transformation to vertices in W } until (no transformation can reduce Δ) until } G. De Micheli, Synthesis and Optimization of Digital G. Circuits, McGraw-Hill, 1994, p. 427. Circuits Spring 2010, Feb 1 Spring ELEC 7770: Advanced VLSI Design (Agrawal) 20 Example of a Transformation (1) a b c 2 1 2 d e 3 2 1 2 x 1 g y 2 Δ = 11 x = a’ + b’ + c’ + d’ + e’ Spring 2010, Feb 1 Spring ELEC 7770: Advanced VLSI Design (Agrawal) 21 Example of a Transformation (2) a b c 2 1 2 d e 3 2 1 2 x Isolate and resynthesize 1 g y 2 Δ = 11 x = a’ + b’ + c’ + d’ + e’, Spring 2010, Feb 1 Spring all inputs are symmetric. ELEC 7770: Advanced VLSI Design (Agrawal) 22 Example of a Transformation (3) d 3 b c 2 a e 1 2 1 2 2 1 2 x 1 y 2 g Δ=8 x = a’ + b’ + c’ + d’ + e’, Spring 2010, Feb 1 Spring a and d are interchanged. ELEC 7770: Advanced VLSI Design (Agrawal) 23 32-bit Ripple-Carry Adder c0 a0 b0 FA0 a1 b1 sum0 sum1 FA1 a2 b2 FA2 sum2 a31 b31 Spring 2010, Feb 1 Spring ELEC 7770: Advanced VLSI Design (Agrawal) FA31 sum31 c31 24 One-bit Full-Adder Circuit ci ai bi Spring 2010, Feb 1 Spring FAi XOR AND sumi XOR AND ELEC 7770: Advanced VLSI Design (Agrawal) OR Ci+1 25 Speeding Up the Adder b0-b15 cin a16-a31 b16-b31 0 a16-a31 b16-b31 1 Spring 2010, Feb 1 Spring 16-bit ripple carry adder 16-bit ripple carry adder 16-bit ripple carry adder sum0-sum15 0 Multiplexer a0-a15 sum16-sum31, c31 1 This is a carry-select adder ELEC 7770: Advanced VLSI Design (Agrawal) 26 ...
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This note was uploaded on 09/16/2011 for the course ELEC 7770 taught by Professor Agrawal,v during the Spring '08 term at Auburn University.

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