Unformatted text preview: ELEC 7770 Advanced VLSI Design Spring 2010
Retiming
Vishwani D. Agrawal
James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 [email protected]
http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr10/course.html
Spring 2010, Feb 5 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 1 Retiming Retiming is a functionpreserving transformation Retiming of a synchronous sequential circuit. of Flipflops are moved according to specific rules. Original references: C. E. Leiserson, F. Rose and J. B. Saxe, “Optimizing C. Synchronous Circuits by Retiming,” Proc. 3rd Caltech Proc. Conf. on VLSI, 1983, pp. 87116. Conf. C. E. Leiserson and J. B. Saxe, “Retiming C. Synchronous Circuitry,” Algorithmica, vol. 6, pp. 535, Algorithmica vol. 1991. 1991.
ELEC 7770: Advanced VLSI Design (Agrawal) 2 Spring 2010, Feb 5 . . . Spring A Trivial Example: Reduced Hardware
FF FF FF Spring 2010, Feb 5 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 3 Example 2: Faster Clock
FF FF Spring 2010, Feb 5 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 4 Example 3: Reduced FlipFlops
FF FF FF Spring 2010, Feb 5 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 5 Applications of Retiming Performance optimization Area optimization Power optimization Testability enhancement FPGA optimization Spring 2010, Feb 5 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 6 Fundamental Operation of Retiming A retiming move in a circuit is caused by moving retiming
all of the memory elements at the input of a combinational block to all of its outputs, or vicecombinational versa.
FF Combinational logic FF ≡ Combinational logic FF Spring 2010, Feb 5 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 7 A Correlator Circuit
+ + + Adder delay = 7 PO host PI = = = = a1 Flipflop
Spring 2010, Feb 5 . . . Spring a2 a3 Comparator delay = 3 a4 ELEC 7770: Advanced VLSI Design (Agrawal) 8 Graph Model
g 0 h 0 1 3 a 7 0 3 b 0 f 7 0 3 c 0 e 7 0 0 1 1 1 3 d Vertex, vi, combinational, delay = d(vi), assumed unchanged by retiming d(host) = 0 Edge, e(vi,vj) or eij, weight wij = number of flipflops between vi and vj
Spring 2010, Feb 5 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 9 Path Delay and Path Weight A set of connected nodes specify a path. A path set does not traverse through the host node. does Path delay = ∑ d(vi) = combinational delay of path Path d(vi) Path weight = ∑ wij = clock delay of path Retiming of a node i is denoted by an integer ri IIt represents the number of registers moved across, t initially ri = 0 initially Register moved from output to input, ri → ri + 1 Register moved from input to output, ri → ri – 1 After retiming, edge weight wij’ = wij + rj – ri
ELEC 7770: Advanced VLSI Design (Agrawal) Spring 2010, Feb 5 . . . Spring 10 Example of Node Retiming
r1 = 0 3 r2 = 0 3 r3 = 0 3 r4 = 0 3 r5 = 0 3 r6 =0 3 ∑ d(vi) = 12, ∑ wij = 0 r1 = 0 3 r2 = 1 3 r3 = 0 3 r4 = 0 3 r5 = 1 3 r6 =0 3 ∑ d(vi) = 12, ∑ wij = 2 Spring 2010, Feb 5 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 11 Legal Retiming Retiming is legal if the retimed circuit has no Retiming negative weights. negative A llegally retimed circuit is functionally equivalent egally to the original circuit – proof by Leiserson and Saxe (1991) Saxe Retiming is the most general method for Retiming changing the register count and position without knowing the functions of vertices. knowing Spring 2010, Feb 5 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 12 Example
a b d 0 host c 0 0
Spring 2010, Feb 5 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 13 c FF x 1 x Example: Illegal Retiming
0 0 host 0 0 Retiming vector = {0, 0, 0} a b d
Spring 2010, Feb 5 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 14 c 0 1 x 0 host 0 0 0 c 0 → –1 1→0 x 0 → –1 0 →1 Retiming vector = {0, 0, –1} c x FF Example: Legal Retiming
0 0 host 0 c 0 0 →1 1 x 0 0 →1 host 0 c 0 1→0 x 0 0 Retiming vector = {0, 0, 0} 0 Retiming vector = {0, 1, 0} a FF FF c b d x Spring 2010, Feb 5 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 15 Correlator Circuit
g 0 h rh=0 0 1 3 7 rg=0 0 3 b rb=0 0 3 c rc=0 0 f 7 rf=0 Critical path delay = 24 e 0 7 re=0 0 0 ra=0 a 1 1 1 3 d rd=0 Initial retiming vector = {0,0,0,0,0,0,0,0} Spring 2010, Feb 5 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 16 Retimed Correlator Circuit
g 0 h rh=0 0 1→0 3 7 0→1 rg=0 0→1 Critical path delay = 13 e 0→1 7 7 re= 2 rf= 1 0 0 0 f 3 b 1→0 rb= 1 3 1 3 d ra= 1 a 1 c rc= 2 rd= 2 retiming vector = {1,1,2,2,2,1,0,0} Spring 2010, Feb 5 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 17 Retiming Theorem Given a network G(V, E, W) and a cycle time T, Given
(r1, . . . ) is a feasible retiming if and only if: (r1, 1. ri – rj ≤ wij for all edges (vi,vj) ε E ri wij for 2. ri – rj ≤ W(vi,vj) – 1 for all nodepairs vi, vj such that ri for
D(vi,vj) > T Where, W(vi,vj): Spring 2010, Feb 5 . . . Spring iis the minimum weight for all paths s between vi and vj between D(vi,vj): iis the maximum delay among all s minimum weight paths between vi and vj between
ELEC 7770: Advanced VLSI Design (Agrawal) 18 Proof of Condition 1 We assume that the original network is legal, i.e., all We edge weights are positive. edge For an arbitrary edge (vi,vj) ε E: For
ri – rj ≤ wij or wij + rj – ri ≥ 0, means that after retiming the new ri weight wij’ = wij + rj – ri will be positive. Thus, condition 1 ensures the legality of retiming. ensures Spring 2010, Feb 5 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 19 Proof of Condition 2 Given: d(vi) < T, for all i. Any retimed path whose combinational delay exceeds Any clock period, will have at least one flipflop. clock The above is the requirement for correct operation.
ri flipflops i Wij flipflops rj flipflops j Path (i,j), D(i,j) > T Original weight, Wij Retimed weight, Wij’ = Wij + rj – ri ≥ 1
Spring 2010, Feb 5 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 20 References Two papers by Leiserson ett al. (see slide 2). Two e G. De Micheli, Synthesis and Optimization of G. Digital Circuits, New York: McGrawHill, 1994. Digital N. Maheshwari and S. S. Sapatnekar, Timing N. Analysis and Optimization of Sequential Circuits, Analysis Boston: Springer, 1999. Boston: Spring 2010, Feb 5 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 21 ...
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