Unformatted text preview: ELEC 7770 Advanced VLSI Design Spring 2010
Constraint Graph and Retiming Solution
Vishwani D. Agrawal
James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 [email protected]
http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr10/course.html
Spring 2010, Feb 10 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 1 Retiming Theorem Given a network G(V, E, W) and a cycle time T, Given
(r1, . . . ) is a feasible retiming if and only if: (r1, ri – rj ≤ wij for all edges (vi,vj) ε E ri wij for ri – rj ≤ W(vi,vj) – 1 for all nodepairs vi, vj such that ri for D(vi,vj) > D(vi,vj) T Where, W(vi,vj) is the minimum weight path between W(vi,vj) vii and vj v D(vi,vj) is the maximum delay among all D(vi,vj)
ELEC 7770: Advanced VLSI Design (Agrawal) Spring 2010, Feb 10 . . . Spring 2 Retiming Theorem Explained Retiming Condition 1, ri – rj ≤ wij is related to edge weight: Condition wij Original circuit is feasible => original weight wij is positive Originally, ri = rj = 0 Retiming, rj flipflops added to eij, ri flipflops removed Retiming, from eij, net reduction ri – rj must be less than wij to leave the retimed weight of eij positive. the Condition 2, ri – rj ≤ W(vi,vj) – 1 is related to path Condition
delays between node pairs being less than clock period T whenever path weight is 0. period Spring 2010, Feb 10 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 3 Timing Optimization Find the clock period (T) by path analysis. Set clock period to T/2 and find a feasible Set retiming. retiming. If feasible, further reduce the clock period to If half. half. If not feasible, increase clock period. Do a binary search for optimum clock period. Retime the circuit.
ELEC 7770: Advanced VLSI Design (Agrawal) 4 Spring 2010, Feb 10 . . . Spring Representing a Constraint
ri – rj ≤ wij or rj ≥ ri – wij rj – wij ri Spring 2010, Feb 10 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 5 Constraint Graph
6 r1 ≥ r0 + 3 r1 ≥ r2 + 1 r2 ≥ r0 + 1 r2 ≥ r1 – 1 r3 ≥ r1 + 1 r3 ≥ r2 + 4 r0 ≥ r3 – 6 r1 3 1 r0 1 1 r3 1 r2 4 Spring 2010, Feb 10 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 6 Feasibility Condition A set of values for variables can be found if and set only if the constraint graph has no positive cycles. cycles. This is also the condition for the solvability of the This longest path problem, which provides a solution to the set of constraints. to Spring 2010, Feb 10 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 7 Example: Infeasible Constraints
x1 ≥ x2 + 6 x2 ≥ x1 – 3 6 x1 3 3 Positive cycle mean no longest path can be found. x1 ≥ x2 + 6 0 3 6 x1 x2 x2 x2 ≥ x1 – 3 Spring 2010, Feb 10 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 8 Solving a Constraint Set
6 r1 ≥ r0 + 3 r1 ≥ r2 + 1 r2 ≥ r0 + 1 r2 ≥ r1 – 1 r3 ≥ r1 + 1 r3 ≥ r2 + 4 r0 ≥ r3 – 6 r1 3 1 r0 1 1 r3 Longest paths from source r0 1 to r0, r1, r2, r3 Path lengths: s0=0, s1=3, s2=2, s3=6 Solution: r0=0, r1=3, r2=2, r3=6
Spring 2010, Feb 10 . . . Spring 4 r2 ELEC 7770: Advanced VLSI Design (Agrawal) 9 The General Path Problem Find the shortest (or longest) path in a graph Find from a source vertex to all other vertices. from Graph has vertices and directed edges: Edge weights can be positive or negative Graph can be cyclic Single source vertex – a vertex with 0 indegree (not Single
a necessary condition) necessary Inconsistent problems Negative weight cycles for shortest path Positive weight cycles for longest path
Spring 2010, Feb 10 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 10 Dijkstra’s Shortest Path Algorithm Greedy algorithm. Applies to directed acyclic graphs (DAG) with positive Applies positive edge weights. edge Computational complexity O(E + V log V) ≤ O(n2) O(E O(n References: A. Aho, J. Hopcroft and J. Ullman, Data Structures and A.
Algorithms, Reading, Massachusetts: AddisonWesley, 1983. Algorithms T. Cormen, C. Leiserson and R. Rivest, Introduction to T. Algorithms, New York: McGrawHill, 1990. Algorithms Spring 2010, Feb 10 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 11 Dijkstra’s Shortest Path Algorithm Dijkstra’s Example 1 Example
w01=15 v0 source 2 v2 v1 10 6 3 v3 Alg. steps s0 s1 s2 s3 ∞ 8 8 8 Initially: mark v0 0 Step 1: mark v2 Step 2: mark v3 Step 3: mark v1 0 0 0 15 2 12 2 11 2 11 2 si = path weight (v0, vi) Each step marks the path with smallest weight and updates the unmarked path weights.
Spring 2010, Feb 10 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 12 Dijkstra’s Shortest Path Algorithm Dijkstra’s Example 2 Example
w01=15 v0 source 2 v2 v1 6 10 3 v3 Alg. steps s0 s1 s2 s3 ∞ 12 12 12 Initially: mark v0 0 Step 1: mark v2 Step 2: mark v1 Step 3: mark v3 0 0 0 15 2 8 8 8 2 2 2 si = path weight (v0, vi) Each step marks the path with smallest weight and updates the unmarked path weights.
Spring 2010, Feb 10 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 13 Dijkstra’s Algorithm, G(V, E, W)
s0(1) = 0 for ( i = 1 to n ) si(1) = w0i repeat {
Mark vq Mark initialize source initialize path weights, n=V –1 Select an unmarked vertex vq such that sq is minimal Select foreach ( unmarked vertex vi ) si = min { si, sq + wqi } } until (all vertices are marked)
Spring 2010, Feb 10 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 14 Try Dijkstra’s Algorithm for Your Graph http://www.dgp.toronto.edu/people/JamesStewart/270/9798s/Laffra/DijkstraApplet.html Spring 2010, Feb 10 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 15 Dijkstra’s Longest Path Algorithm
w01=15 v0 source 2 v2 w01= 15 v0 source 2 v2 v1 10 6 v1 10 6 3 v3 Either change min to max Or change all positive weights to negatives Alg. steps Initially s0 0 s1 s2 s3 ∞ ∞ 8 8
16 15 2 15 2 15 2 15 2 3 v3 Step 1: mark v1 0 Step 2: mark v2 0 Step 3: mark v3 0
ELEC 7770: Advanced VLSI Design (Agrawal) si = path length (v0, vi)
Spring 2010, Feb 10 . . . Spring Dijkstra’s Alg. Does Not Work for Dijkstra’s Cycles, Mixed Weights Cycles,
2 w01=15 v0 source 2 v2 v1 5 4 3 v3 Alg. steps s0 s1 15 7 7 7 s2 2 2 2 2 s3 ∞ 6 6 6? Initially: mark v0 0 Step 1: mark v2 0 Step 2: mark v3 0 Step 3: mark v1 0 si = path weight (v0, vi) Algorithm stops because all vertices are marked. But, there exists a v0 to v3 path of length 5
Spring 2010, Feb 10 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 17 Bellman’s Equations – Shortest Path
vj wji vi vm wmi wni vn vk wki For all vertices: si = min (sq + wqi) vq ε pred(vi) sq = minimum path weight between source and vq
ELEC 7770: Advanced VLSI Design (Agrawal) 18 Spring 2010, Feb 10 . . . Spring BellmanFord Algorithm, G(V, E, W)
BellmanFord { s0(1) = 0 for ( i = 1 to n )
si(1) = w0i initialize source initialize path weights, n = V – 1 n iterations
min { si(j), sk(j) + wkj } vk ε pred(vi) for ( j = 1 to n )
for ( i = 1 to n )
si(j+1) = } iif ( si(j+1) == si(j) ∀i ) return (true) f } return (false)
Spring 2010, Feb 10 . . . Spring Complexity = O(VE) ≤ O(n3)
ELEC 7770: Advanced VLSI Design (Agrawal) 19 BellmanFord Shortest Path
n=3 w01=15 v0 source 2 v2 v1 10 6 3 v3 Alg. steps Initially Iteration 1 Iteration 2 Iteration 3 s0 0 0 0 0 s1 s2 s3 ∞ 8 8 8 15 2 12 2 11 2 11 2 si = path weight (v0, vi) Spring 2010, Feb 10 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 20 BellmanFord Longest Path
Reverse the sign of weights and solve shortest path problem. (Alternative: keep original weights and change min operator in algorithm to max.) n = 3 (shortest path) Weights reversed w01= 15 v0 source 2 v1 10 v2 6 Alg. steps Initially s0 0 0 0 s1 s2 s3 ∞ 8 8 3 v3 15 2 15 2 15 2 Iteration 1 Iteration 2 si = path weight (v0, vi) Spring 2010, Feb 10 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 21 Bellman’s Equations – Longest Path
vj wji vi vm wmi wni vn vk wki For all vertices: si = max (sq + wqi) vq ε pred(vi) sq = maximum path weight between source and vq
ELEC 7770: Advanced VLSI Design (Agrawal) 22 Spring 2010, Feb 10 . . . Spring BellmanFord for Cycles, Neg. Weights
w01=15 v0 source 2 v2 v1 5 4 2 3 v3 n = 3 (shortest path) Alg. steps Initially Iteration 1 Iteration 2 Iteration 3 s0 0 0 0 0 s1 s2 s3 ∞ 6 5 5 15 2 7 7 7 2 2 2 si = path weight (v0, vi) This was incorrect with Dijkstra’s shortest path algorithm
Spring 2010, Feb 10 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 23 BellmanFord for Negative Cycle
w01=15 v0 source 2 v2 v1 5 4 2 3 v3 n = 3 (shortest path) Alg. steps Initially Iteration 1 Iteration 2 Iteration 3 s0 0 0 0 0 s1 s2 s3 ∞ 6 6 5 15 2 7 3 3 2 2 2 si = path weight (v0, vi) Values not stabilized after n iterations. Inconsistent problem: negative cycle.
Spring 2010, Feb 10 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 24 Retiming Example 10 a 5 b FF 5 c Delay Spring 2010, Feb 10 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 25 Retiming Graph
10 a 5 b FF 5 c 1 h 0 0 a 10 0 b 5 1 c 5 Critical path = 15 It is the longest path consisting only of zero weight edges.
Spring 2010, Feb 10 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 26 Feasibility Constraints (Condition 1)
10 a 5 b FF 5 c 1 h 0 0 a 10 0 b 5 1 c 5 ri – rj ≤ wij ∀ edges i → j Retiming should not cause negative edge weights.
Spring 2010, Feb 10 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) rh – ra ≤ 0 ra – rb ≤ 0 rb – rc ≤ 1 rc – rh ≤ 1
27 Constraint Graph
10 a 5 b 1 FF 5 c rh 0 0 ra 10 0 rb 5 1 rc 5 rh – ra ≤ 0 ra – rb ≤ 0 Constraints for rb – rc ≤ 1 Condition 1 rc – rh ≤ 1 Observation: Constraint graph has the same structure as the original retiming graph, with signs of weights reversed. Vertex labels are the retiming integer variables. ri – rj ≤ wij ∀ edges i → j Retiming should not cause negative edge weights.
Spring 2010, Feb 10 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 28 Max Delay for Min Weight Paths
1 h 0 0 a 10 T = 15 W(h,a) = 0 W(h,b) = 0 W(h,c) = 1 W(a,b) = 0 W(a,c) = 1 W(a,h) = 2 D(h,a) = 10 D(h,b) = 15 D(h,c) = 20 D(a,b) = 15 D(a,c) = 20 D(a,h) = 20 W(b,c) = 1 W(b,h) = 2 W(b,a) = 2 W(c,h) = 1 W(c,a) = 1 W(c,b) = 1 D(b,c) = 10 D(b,h) = 10 D(b,a) = 20 D(c,h) = 5 D(c,a) = 15 D(c,b) = 20 0 b 5 1 c 5 Spring 2010, Feb 10 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 29 Timing Optimization, T = 7.5?
1 Constraint graph (feasibility) rb 5 1 rc 5 0 0 rh 0 ra 10 Add constraints for Condition 2: ri – rj ≤ W(I,j) – 1 W(h,a) = 0 W(h,b) = 0 W(h,c) = 1 W(a,b) = 0 W(a,c) = 1 W(a,h) = 2
Spring 2010, Feb 10 . . . Spring ∀ paths (i,j) such that D(i,j) > 7.5 W(b,c) = 1 W(b,h) = 2 W(b,a) = 2 W(c,h) = 1 W(c,a) = 1 W(c,b) = 1 D(b,c) = 10 D(b,h) = 10 D(b,a) = 20 D(c,h) = 5 D(c,a) = 15 D(c,b) = 20
30 D(h,a) = 10 D(h,b) = 15 D(h,c) = 20 D(a,b) = 15 D(a,c) = 20 D(a,h) = 20 ELEC 7770: Advanced VLSI Design (Agrawal) Timing Optimization, T = 7.5?
1 1 rh 0 0 1 1 W(h,a) = 0 W(h,b) = 0 W(h,c) = 1 W(a,b) = 0 W(a,c) = 1 W(a,h) = 2
Spring 2010, Feb 10 . . . Spring 0 1 ra 10 0 D(h,a) = 10 D(h,b) = 15 D(h,c) = 20 D(a,b) = 15 D(a,c) = 20 D(a,h) = 20 W(b,c) = 1 W(b,h) = 2 W(b,a) = 2 W(c,h) = 1 W(c,a) = 1 W(c,b) = 1 0 1 1 rb 5 0 0 1 0 rc 5 Positive cycle; no solution for longest path D(b,c) = 10 D(b,h) = 10 D(b,a) = 20 D(c,h) = 5 D(c,a) = 15 D(c,b) = 20
31 ELEC 7770: Advanced VLSI Design (Agrawal) Timing Optimization, T = 11.25?
1 1 rh 0 0 1 ra 10 0 W(h,a) = 0 W(h,b) = 0 W(h,c) = 1 W(a,b) = 0 W(a,c) = 1 W(a,h) = 2
Spring 2010, Feb 10 . . . Spring 1 0 1 rb 5 0 0 0 1 rc 5 rh = 0 rb = 1 rc = 0 ra = 0 D(h,a) = 10 D(h,b) = 15 D(h,c) = 20 D(a,b) = 15 D(a,c) = 20 D(a,h) = 20 W(b,c) = 1 W(b,h) = 2 W(b,a) = 2 W(c,h) = 1 W(c,a) = 1 W(c,b) = 1 D(b,c) = 10 D(b,h) = 10 D(b,a) = 20 D(c,h) = 5 D(c,a) = 15 D(c,b) = 20
32 ELEC 7770: Advanced VLSI Design (Agrawal) Retiming Graph
10 a 5 b FF 5 c 1 h 0 rh = 0 0 a 10 ra = 0 0 1 b 5 rb = 1 1 0 c 5 rc = 0 wij_retimed = wij + rj – ri
Spring 2010, Feb 10 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 33 Retimed Circuit
10 a FF 5 b 5 c 1 Logic optimization will remove these. b 5 rb = 1 0 c 5 rc = 0 Critical Path = 10 h 0 rh = 0 0 a 10 ra = 0 1 Spring 2010, Feb 10 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 34 Reference Reference
G. De Micheli, Synthesis and Optimization G. of Digital Circuits, New York: McGrawHill, of New 1994. 1994. Spring 2010, Feb 10 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 35 ...
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 Shortest path problem, Ri, Longest path problem, Vishwani D. Agrawal, Advanced VLSI Design, j Retiming

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