lec8_skew - ELEC 7770 Advanced VLSI Design Spring 2010...

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Unformatted text preview: ELEC 7770 Advanced VLSI Design Spring 2010 Clock Skew Problem Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 vagrawal@eng.auburn.edu http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr10/course.html Spring 2010, Feb 19 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 1 Single Clock Data_in Data_out Comb. CKA FF A CKB FF B CK CKA CKB Single-cycle path delay Spring 2010, Feb 19 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 2 Multiple Clocks Data_in Data_out Comb. FF A CKA FF B CKB CKA CKB Multi-cycle path delay Spring 2010, Feb 19 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 3 Clock Skew Skew is the time delay of clock signal at a flip flop with respect to some time reference. For a given layout each flip-flop has a skew, For measured with respect to the a common reference. reference. Skews of flip-flops separated by combinational Skews paths affect the short-path and long-path constraints. constraints. Spring 2010, Feb 19 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 4 Skews for Single-Cycle Paths FFi CKi Combinational Block Delay: δ(i,j) ≤ d(i,j) ≤ Δ(i,j) xi FFj CKj xj xi and xj are arrival times of clock edges Spring 2010, Feb 19 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 5 Short-Path Constraint (Double-Clocking) Tck CKi si Not intended CKj intended Thj sj δ(i,j) si + δ(i,j) ≥ sj + Thj Spring 2010, Feb 19 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 6 Long-Path Constraint (Zero-Clocking) Tck CKi si intended Not intended CKj sj Tsj Δ(i,j) si + Δ(i,j) ≤ sj + Tck – Tsj Spring 2010, Feb 19 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 7 Maximum Clock Frequency Linear program: Minimize Tck Subject to: For all flip-flop pairs (i,j), si + δ(i,j) ≥ sj + Thj si + Δ(i,j) ≤ sj + Tck – Tsj Spring 2010, Feb 19 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 8 Finding Clock Skews sk si FFi Ri FFj Rj FFk Rk CK Ci Cj Ck sj Use Elmore delay formula to calculate si, sj, sk. Spring 2010, Feb 19 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 9 Interconnect Delay: Elmore Delay Model W. Elmore, “The Transient Response of Damped Linear Networks with W. Particular Regard to Wideband Amplifiers,” J. Appl. Phys., vol. 19, J. ., no.1, pp. 55-63, Jan. 1948. no.1, CK Shared resistance: Rii = Ri Rij = Rji = Ri Rik = Rki = Ri Rjj = Ri + Rj Rjk = Rkj = Ri + Rj Rkk = Ri + Rj + Rk Spring 2010, Feb 19 . . . Spring Ri i Rj Ci Rk j Cj ELEC 7770: Advanced VLSI Design (Agrawal) k Ck 10 Elmore Delay Calculation Delay at node k, sk = 0.69 (Ci × Rik + Cj × Rjk + Ck × Rkk ) = 0.69 [Ri Ci + (Ri + Rj) Cj + (Ri + Rj + Rk)Ck] Spring 2010, Feb 19 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 11 Finding δ(I,j) and Δ(I,j) Finding (I,j) Minimum delay Maximum delay ∞ , -∞ ∞ , -∞ A 1 ∞ , -∞ ∞ , -∞ 0, 0 B 3 3, 3 i ∞ , -∞ ∞ , -∞ ∞ , -∞ ∞ , -∞ Spring 2010, Feb 19 . . . Spring H 9, 10 j 3 E 1 4, 4 G 2 C 1 ∞ , -∞ D 2 ∞ , -∞ F 1 5, 5 ELEC 7770: Advanced VLSI Design (Agrawal) 6, 7 J 6, 8 1 k 12 Maximum Clock Frequency for Maximum Tolerance ±q/2 in Skew ±q/2 Linear program: Minimize Tck Subject to: For all flip-flop pairs (i,j), si + δ(i,j) ≥ sj + Thj + q si + Δ(i,j) ≤ sj + Tck – Tsj – q Where q is a constant si are variables, simin ≤ si Tck is a variable Spring 2010, Feb 19 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 13 Maximum Tolerance for Given Clock Maximum Frequency Frequency Linear program: Maximize q Subject to: For all flip-flop pairs (i,j), si + δ(i,j) ≥ sj + Thj + q si + Δ(i,j) ≤ sj + Tck – Tsj – q Where Tck is a constant si are variables, simin ≤ si q is a variable Spring 2010, Feb 19 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 14 No solution because of zero slack. Increasing skew tolerance q Tradeoffs Increasing clock period Tck Spring 2010, Feb 19 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 15 Clock Skew Problem N. Maheshwari and S. S. Sapatnekar, Timing Analysis and Optimization of Sequential Circuits, Springer, 1999. J. P. Fishburn, “Clock Skew Optimization,” IEEE J. Trans. Computers, vol. 39, no. 7, pp. 945-951, Trans. vol. July 1990. July Spring 2010, Feb 19 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 16 ...
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