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Unformatted text preview: ELEC 7770 Advanced VLSI Design Spring 2010 Linear Programming – A Mathematical Optimization Technique Optimization Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 vagrawal@eng.auburn.edu http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr10/course.html Spring 2010, Feb 22 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 1 What is Linear Programming Linear programming (LP) is a mathematical method for selecting the best solution from the available solutions of a problem. Method: State the problem and define variables whose values will be determined. Develop a linear programming model: Write the problem as an optimization formula (a An available LP solver (computer program) gives the values of variables. Spring 2010, Feb 22 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 2 linear expression to be minimized or maximized) Write a set of linear constraints Types of LPs LP – all variables are real. ILP – all variables are integers. MILP – some variables are integers, others are real. A reference: S. I. Gass, An Illustrated Guide to Linear Programming, New York: Dover, 1990. Spring 2010, Feb 22 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 3 A Single-Variable Problem Consider variable x Problem: find the maximum value of x subject to constraint, 0 ≤ x ≤ 15. Solution: x = 15. Constraint satisfied 0 15 Solution x = 15 Spring 2010, Feb 22 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 4 x Single Variable Problem (Cont.) Consider more complex constraints: Maximize x, subject to following constraints: 0 x≥0 5x ≤ 75 6x ≤ 30 x ≤ 10 5 (3) All constraints satisfied Solution, x = 5 Spring 2010, Feb 22 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 5 (1) (2) (3) (4) 10 (4) 15 (2) x (1) A Two-Variable Problem Manufacture of chairs and tables: Resources available: Material: 400 boards of wood Labor: 450 man-hours Profit: Chair: $45 Table: $80 Resources needed: Chair 5 boards of wood 10 man-hours Table 20 boards of wood 15 man-hours Problem: How many chairs and how many tables should be manufactured to maximize the total profit? ELEC 7770: Advanced VLSI Design (Agrawal) 6 Spring 2010, Feb 22 . . . Spring Formulating Two-Variable Problem Manufacture x1 chairs and x2 tables to maximize profit: P = 45x1 + 80x2 dollars Subject to given resource constraints: 5x1 + 20x2 ≤ 400 400 boards of wood, 450 man-hours of labor, 10x1 + 15x2 ≤ 450 x1 ≥ 0 x2 ≥ 0 Spring 2010, Feb 22 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) (1) (2) (3) (4) 7 Solution: Two-Variable Problem P = 22 00 30 40 Ma n -p Tables, x2 ow e rc (1) 20 10 (3) 0 on str Best solution: 24 chairs, 14 tables Profit = 45×24 + 80×14 = 2200 dollars a in t (24, 14) Mate ria l con strain t P = 0 (4) decresing Spring 2010, Feb 22 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) Pr ofi t 0 10 20 30 40 50 60 70 80 90 Chairs, x1 increasing (2) 8 Change Profit of Chair to $64/Unit Manufacture x1 chairs and x2 tables to maximize profit: P = 64x1 + 80x2 dollars Subject to given resource constraints: 5x1 + 20x2 ≤ 400 400 boards of wood, 450 man-hours of labor, 10x1 + 15x2 ≤ 450 x1 ≥ 0 x2 ≥ 0 Spring 2010, Feb 22 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) (1) (2) (3) (4) 9 Solution: $64 Profit/Chair P = 2 8 80 40 Ma n-p 30 owe rc Tables, x2 (1) 20 10 0 on s tra int Best solution: 45 chairs, 0 tables Profit = 64×45 + 80×0 = 2880 dollars P = 0 (24, 14) (3) (4) Mate rial c onstr aint Spring 2010, Feb 22 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) Pr ofi t 0 10 20 30 40 50 60 70 80 90 Chairs, x1 (2) increasing decresing 10 A Dual Problem Explore an alternative. Questions: Should we make tables and chairs? Or, auction off the available resources? To answer this question we need to know: What is the minimum price for the resources that will provide us with same amount of revenue from sale as the profits from tables and chairs? This is the dual of the original problem. Spring 2010, Feb 22 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 11 Formulating the Dual Problem Revenue received by selling off resources: For each board, w1 For each man-hour, w2 Minimize 400w1 + 450w2 Resources: Material: 400 boards Labor: 450 man-hrs Profit: Chair: $45 Table: $80 Resources needed: Chair Table 5 boards of wood 10 man-hours Subject to constraints: 5w1 + 10w2 20w1 + 15w2 ≥0 w1 ≥0 w2 Spring 2010, Feb 22 . . . Spring ≥ 45 ≥ 80 20 boards of wood 15 man-hours ELEC 7770: Advanced VLSI Design (Agrawal) 12 The Duality Theorem IIf the primal has a finite optimum solution, so f does the dual, and the optimum values of the objective functions are equal. objective Reference: G. Strang, Linear Algebra and Its Applications. G. Linear Fort Worth: Harcourt Brace Javanovich College Publishers, third edition, 1988. Publishers, Spring 2010, Feb 22 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 13 Primal-Dual Problems Primal problem Fixed resources Maximize profit Dual Problem Fixed profit Minimize value Variables: x1 (number of chairs) w1 ($ value/board of wood) x2 (number of tables) w2 ($ value/man-hour) Maximize profit 45x1+80x2 Minimize value 400w1+450w2 Subject to: Subject to: ≤ 400 5x1 + 20x2 ≥ 45 5w1 + 10w2 ≤ 450 10x1 + 15x2 20w1 + 15w2 ≥ 80 ≥0 x1 ≥0 w1 ≥0 x2 ≥0 w2 Solution: Solution: x1 = 24 chairs, x2 = 14 tables w1 = $1, w2 = $4 Profit = $2200 value = $2200 Spring 2010, Feb 22 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 14 Variables: LP for n Variables LP n minimize Σ cj xj j =1 n Objective function subject to aij xj ≤ bi, i = 1, 2, . . ., m j =1 n cij xj = di, i = 1, 2, . . ., p j =1 Σ Σ Variables: xj Constants: cj, aij, bi, cij, di Spring 2010, Feb 22 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 15 Algorithms for Solving LP Simplex method G. B. Dantzig, Linear Programming and Extension, Princeton, New G. Linear Princeton, Jersey, Princeton University Press, 1963. Jersey, Ellipsoid method L. G. Khachiyan, “A Polynomial Algorithm for Linear Programming,” L. Soviet Math. Dokl., vol. 20, pp. 191-194, 1984. Soviet Interior-point method N. K. Karmarkar, “A New Polynomial-Time Algorithm for Linear N. Programming,” Combinatorica, vol. 4, pp. 373-395, 1984. Combinatorica Course website of Prof. Lieven Vandenberghe (UCLA), Course http://www.ee.ucla.edu/ee236a/ee236a.html http://www.ee.ucla.edu/ee236a/ee236a.html Spring 2010, Feb 22 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 16 Basic Ideas of Solution methods Extreme points Extreme points Constraints Simplex: search on extreme points. Complexity: polynomial in n, number of variables Spring 2010, Feb 22 . . . Spring Objective function Interior­point methods: Successively iterate with interior spaces of analytic convex boundaries. Complexity: O(n3.5L), L = no. of int. values 17 Constraints Objective function ELEC 7770: Advanced VLSI Design (Agrawal) Integer Linear Programming (ILP) Variables are integers. Complexity is exponential – higher than LP. LP relaxation Convert all variables to real, preserve ranges. LP solution provides guidance. Rounding LP solution can provide a non-optimal Rounding solution. solution. Spring 2010, Feb 22 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 18 Traveling Salesperson Problem (TSP) 12 27 1 18 10 3 15 12 19 2 5 20 4 6 5 Spring 2010, Feb 22 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 19 Solving TSP: Five Cities Distances (dij) in miles (symmetric TSP, general TSP is asymmetric) City i=1 i=1 i=2 i=2 i=3 i=3 i=4 i=4 i=5 i=5 Spring 2010, Feb 22 . . . Spring j=1 j=1 0 18 10 12 27 j=2 j=2 18 0 5 12 20 j=3 10 5 0 15 19 j=4 12 12 15 0 6 j=5 27 20 19 6 0 20 ELEC 7770: Advanced VLSI Design (Agrawal) Search Space: No. of Tours Asymmetric TSP tours Five-city problem: 4 × 3 × 2 × 1 = 24 tours Five-city 24 Ten-city problem: 362,880 tours 15-city problem: 87,178,291,200 tours 50-city problem: 49! = 6.08×1062 tours Time for enumerative search assuming 1 μs Time per tour evaluation = 1.93×1055 years per Spring 2010, Feb 22 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 21 A Greedy Heuristic Solution Tour length = 10 + 5 + 12 + 6 + 27 = 60 miles (non-optimal) City i=1 (start) i=2 i=3 i=4 i=5 Spring 2010, Feb 22 . . . Spring j=1 0 18 10 12 27 j=2 18 0 5 12 20 j=3 10 5 0 15 19 j=4 12 12 15 0 6 j=5 27 20 19 6 0 22 ELEC 7770: Advanced VLSI Design (Agrawal) ILP Variables, Constants and Constraints x14 ε [0,1] d14 = 12 1 4 5 x15 ε [0,1] d15 = 27 x12 ε [0,1] d12 = 18 Integer variables: xij = 1, travel i to j xij = 0, do not travel i to j 2 Real constants: dij = distance from i to j x13 ε [0,1] d13 = 10 3 x12 + x13 + x14 + x15 = 1 four other similar equations Spring 2010, Feb 22 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 23 Objective Function and ILP Solution 5 i-1 Minimize ∑ ∑ xij × dij i=1 j=1 ∑ xij = 1 for all i j≠i xij xij i=1 i=1 2 3 4 5 Spring 2010, Feb 22 . . . Spring j=1 j=1 0 1 0 0 0 2 0 0 1 0 0 3 1 0 0 0 0 4 0 0 0 0 1 5 0 0 0 1 0 24 ELEC 7770: Advanced VLSI Design (Agrawal) ILP Solution d54 = 6 4 d45 = 6 1 d21 = 18 d13 = 10 3 2 d32 = 5 Total length = 45 but not a single tour 25 5 Spring 2010, Feb 22 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) Additional Constraints for Single Tour Following constraints prevent split tours. For any Following subset S of cities, the tour must enter and exit that subset: that ∑ xij ≥ 2 for all S, |S| < 5 iεS jεS Remaining set At least two arrows must cross this boundary. Any subset Spring 2010, Feb 22 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 26 ILP Solution d41 = 12 1 d25 = 20 d13 = 10 3 2 d32 = 5 Total length = 53 4 d54 = 6 5 Spring 2010, Feb 22 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 27 A combinational circuit has n test vectors that detect m combinational ILP Example: Test Minimization faults. Each vector detects a subset of faults. Find the smallest subset of test vectors that each fault is detected by at least N vectors. Simulate vectors without dropping faults. Test vectors T1 F1 F2 1 0 . . 1 . 0 T2 0 0 . . 0 . 1 . 0 1 . . 0 . 1 . 1 1 . . 1 . 1 Tj 1 0 . . 1 . 0 . 0 0 . . 0 . 0 . 1 0 . . 0 . 0 . 0 1 . . 1 . 0 Tn 0 0 . . 1 . 1 28 fij = 1, if test Ti detects fault Fj Faults . . Fj . Fm Spring 2010, Feb 22 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) Test Minimization by ILP Construct an ILP model: 1.Assign an integer variable ti ε [0,1] to ith test vector such that ti = 1, if we select ti, otherwise ti= 0. 2.Define an integer constant fij ε [0,1] such that fij = 1, if ith vector detects jth fault, otherwise fij = 0. Values of constants fij are determined by fault simulation. n minimize ti i=1 n subject to fij ti ≥ N, i=1 Σ Objective function Σ j = 1, 2, . . ., m Spring 2010, Feb 22 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 29 N-Detect Tests (N = 5) Circuit c432 c432 c499 c499 c880 c880 c1355 c1355 c1908 c1908 c2670 c2670 c3540 c3540 c5315 c5315 c6288 c6288 c7552 c7552 Spring 2010, Feb 22 . . . Spring Unoptimized vectors 608 379 1,023 755 1,055 959 1,971 1,079 243 2,165 197 260 127 420 543 477 471 376 57 841 ILP (exact) Minimum vectors CPU s 1.0 2.3 881.8 4.4 6.9 7.2 20008.5 40.7 34740.0 114.3 30 ELEC 7770: Advanced VLSI Design (Agrawal) Why ILP Solution is Exponential? Must try all 2n roundoff points Second variable LP solution found in polynomial time (bound on ILP solution) First variable Spring 2010, Feb 22 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) Constraint s Objective (maximize) 31 Characteristics of ILP Worst-case complexity is exponential in number of Worst-case variables. variables. Linear programming (LP) relaxation, where integer Linear variables are treated as real, gives a lower bound on the objective function. objective Recursive rounding of relaxed LP solution to nearest integers gives an approximate solution to the ILP problem. problem. K. R. Kantipudi and V. D. Agrawal, “A Reduced Complexity K. Algorithm for Minimizing N-Detect Tests,” Proc. 20th International -Detect Proc. Conf. VLSI Design, January 2007, pp. 492-497. Conf. Spring 2010, Feb 22 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 32 Recursive Rounding Algorithm 1. Obtain a relaxed LP solution. Stop if each Obtain 2. 3. 4. variable in the solution is an integer. variable Round the variable closest to an integer. Remove any constraints that are now Remove unconditionally satisfied. unconditionally Go to step 1. Spring 2010, Feb 22 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 33 Complexity of Approximation Recursive rounding: IILP is transformed into k LPs with progressively reducing LP number of variables, where k is the size of the solution. number A solution that satisfies all constraints is guaranteed; this solution solution is often close to optimal. solution Number of LPs, k, is the size of the final solution, i.e., the Number number of non-zero variables in the test minimization problem. problem. Recursive rounding complexity is k × O(np), where k ≤ n, ), n is number of variables. is Spring 2010, Feb 22 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 34 Four-Bit ALU Circuit Initial Initial vectors vectors 285 400 500 1,000 5,000 10,000 16,384 Spring 2010, Feb 22 . . . Spring ILP Vectors 14 13 12 12 12 12 12 CPU s 0.65 1.07 4.38 4.17 12.95 34.61 87.47 Recursive rounding Vectors 14 13 13 12 12 12 12 CPU s 0.42 1.00 3.00 3.00 9.00 17.0 37.0 35 ELEC 7770: Advanced VLSI Design (Agrawal) ILP vs. Recursive Rounding 100 75 ILP Recursive Rounding CPU s 50 25 0 Spring 2010, Feb 22 . . . Spring 0 5,000 ELEC 7770: Advanced VLSI Design (Agrawal) 10,000 15,000 Vectors 36 N-Detect Tests (N = 5) 5) Circuit Unoptimized Unoptimized vectors vectors Relaxed LP/Recur. Relaxed rounding rounding Lower Lower bound bound c432 c432 c499 c499 c880 c880 c1355 c1355 c1908 c1908 c2670 c2670 c3540 c3540 c5315 c5315 c6288 c6288 Spring 2010, Feb 22 . . . Spring ILP (exact) CPU s 1.0 2.3 881.8 4.4 6.9 7.2 20008.5 40.7 34740.0 114.3 37 Min. Min. Min. CPU s Min. vectors vectors vectors vectors 197 260 128 420 543 477 477 377 57 841 1.0 1.2 14.0 3.2 4.6 4.7 72.0 18.0 39.0 52.0 197 260 127 420 543 477 471 376 57 841 608 379 1,023 755 1,055 959 1,971 1,079 243 2,165 196.38 260.00 125.97 420.00 543.00 477.00 467.25 374.33 52.52 841.00 c7552 c7552 ELEC 7770: Advanced VLSI Design (Agrawal) A Primal-Dual Solution (N = 1) Primal-Dual Circuit Name Lower bound on vectors Recursive LP minimization Unopt. vectors LP CPU s Minimized vectors Primal-dual minimization Unopt. vectors Total CPU s Minimized vectors c432 27 608 2.00 36 983 5.52 31 c499 52 379 1.00 52 221 1.35 52 c880 13 1023 31.00 28 1008 227.21 25 c1355 84 755 5.00 84 507 1.95 84 c1908 106 1055 8.00 107 728 2.50 107 c2670 44 959 9.00 84 1039 17.41 79 c3540 78 1971 197.00 105 2042 276.91 95 c5315 37 1079 464.00 72 1117 524.53 67 c6288 6 243 78.00 18 258 218.9 17 M. A. Shukoor and V. D. Agrawal, “A Primal-Dual Solution to Minimal Test 139 c7552 65 2165 151.00 145 2016 71.21 Generation Problem,” Proc. 12th IEEE VLSI Design & Test Symp. (VDAT08), 2008, pp.Spring 2010, Feb 22 . . . 269-279. ELEC 7770: Advanced VLSI Design (Agrawal) 38 Finding LP/ILP Solvers R. Fourer, D. M. Gay and B. W. Kernighan, AMPL: A Modeling R. Language for Mathematical Programming, South San Francisco, Language South California: Scientific Press, 1993. Several of programs described in this book are available to Auburn users. this B. R. Hunt, R. L. Lipsman, J. M. Rosenberg, K. R. Coombes, J. E. B. Osborn and G. J. Stuck, A Guide to MATLAB for Beginners and Experienced Users, Cambridge University Press, 2006. Experienced Search the web. Many programs with small number of variables can Search be downloaded free. be Spring 2010, Feb 22 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 39 A Circuit Optimization Problem Circuit Given: Circuit netlist Cell library with multiple versions for each cell Select cell versions to optimize a specified Select characteristic of the circuit. Typical characteristics are: characteristics Area Power Delay ELEC 7770: Advanced VLSI Design (Agrawal) 40 Spring 2010, Feb 22 . . . Example: Cell(X), X = 0 or 1 Example: X=0 Delay = d Power = 3 × p Power X=1 Delay = 2 × d Delay Power = 0.5 × p Power Cell delay = (1 – X) d + 2 X d Power = 3(1 – X) p + 0.5 X p Spring 2010, Feb 22 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 41 ILP Model: Minimum Power & Delay ILP Arrival time = T1 Ti kth Cell Arrival time = Tk Ti = signal arrival time at ith input; Ti = 0 for all PIs Tk = signal arrival time at cell output Tk ≥ Ti + (1 – Xk) dk + 2 Xk dk, for all i Tk (1 Where, dk = nominal delay of gate Where, dk Xk = 0 or 1, specifies version of cell Minimize α TPO + ∑ [3(1 – Xk) pk + 0.5 Xk pk] Minimize all k all Spring 2010, Feb 22 . . . ELEC 7770: Advanced VLSI Design (Agrawal) α is constant 42 Given Clock Specification Given Tj = 0, for all primary inputs j Tk ≤ clock period, for all primary outputs k Tk clock Tk ≥ Ti + (1 – Xk) dk + 2 Xk dk, for all gates k Tk with input i with Register Combinational Logic Clock Spring 2010, Feb 22 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 43 Register Minimum Power Design Minimum Minimize ∑ all k where pk = nominal power consumption of pk kth cell kth 3(1 – Xk) pk + 0.5 Xk pk Spring 2010, Feb 22 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 44 Logic Minimization Logic Consider a four-variable function, {2,4,6,8,9,10,12,13,15} Karnaugh map shows prime implicants (PI) found by Karnaugh Quine-McCluskey procedure. Quine-McCluskey Find the minimum number of Pis to cover all minterms. A 1 1 1 1 1 1 EPI’s C 1 1 D 1 Non-EPI’s Fall 2008, Oct 13 . . . B Non-EPI’s 45 ELEC2200-002 Lecture 5 Select a Minimal Set of PI’s Select Covered by EPI → Minterm → PI1 PI2 PI3 PI4 PI5 PI6 x x x x x x x x x x x x 2 4 6 x 8 x x 9 x 10 x 12 x x 13 x x 15 1. First PI7 select essential prime implicants (EPIs). 2. Cover remaining minterms with smallest number of prime implicants (Pis). Fall 2008, Oct 13 . . . ELEC2200-002 Lecture 5 46 Cover Remaining Minterms Cover Remaining minterms → PI2 PI3 PI4 PI5 PI6 2 x x x x x x 4 6 x x 10 Integer linear program (ILP): Define integer {0,1} variables, xk = 1, select PIk; xk = 0, do not select PIk. Minimize ∑k xk, subject to following constraints: x2 + x3 ≥ 1 (cover minterm 2) x4 + x5 ≥ 1 (cover minterm 4) x2 + x4 ≥ 1 (cover minterm 6) x3 + x6 ≥ 1 (cover minterm 10) A solution is x3 = x4 = 1, x2 = x5 = x6 = 0 Fall 2008, Oct 13 . . . ELEC2200-002 Lecture 5 47 Minimized Function Minimized F(A,B,C,D) = PI1 + PI3 + PI4 + PI7 PI7 = AC +B CD +A BD + A B D A 1 1 1 1 1 1 EPI’s in MSOP C 1 1 D 1 Selected PIs Fall 2008, Oct 13 . . . B Pis not selected 48 ELEC2200-002 Lecture 5 Comb. Circuit Power Optimization Given a set of test vectors Reorder vectors to minimize the number of Reorder transitions at primary inputs transitions 01010101 00110011 00001111 11 transitions Combinational circuit (tested by exhaustive vectors) 01111000 Rearranged vector set 00110011 00011110 Copyright Agrawal, 2007 Copyright produces 7 transitions 49 ELEC6270 Spring 09, Lecture 10 Reducing Comb. Test Power Reducing Original tests: V1 V2 V3 V4 V5 11 00 0 10 10 0 10 10 1 10 11 1 10 input transitions Reordered tests: V1 V3 V5 V4 V2 10 00 1 11 00 0 11 10 0 11 11 0 5 input transitions Copyright Agrawal, 2007 Copyright 1 V1 3 V4 3 V2 2 1 3 V5 2 Traveling salesperson problem (TSP) finds the shortest distance closed path (or cycle) to visit all nodes exactly once. But, we need an open loop solution. 4 V3 1 2 ELEC6270 Spring 09, Lecture 10 50 Open-Loop TSP Open-Loop 1 0 V0 0 V1 0 0 3 V4 0 3 V2 2 1 3 V5 4 V3 1 2 2 Add a node V0 at distance 0 from all other nodes. Solve TSP for the new graph. Delete V0 from the solution. Copyright Agrawal, 2007 Copyright ELEC6270 Spring 09, Lecture 10 51 Combinational Vector Ordering Combinational See: P. Wray, “Minimize test power for benchmark circuit c6288 by Minimize optimal ordering of vectors,” ELEC 6270 Class Project Report, Spring 2009, www.eng.auburn.edu/~vagrawal/COURSE/E6270_Spr09/PROJECT/WRAY/ www.eng.auburn.edu/~vagrawal/COURSE/E6270_Spr09/PROJECT/WRAY/ TSP has exponential complexity; good heuristics are available. For other extensions: V. Dabholkar, S. Chakravarty, I Pomeranz and S. Reddy, V. “Techniques for Minimizing Power Dissipation in Scan and Combinational Circuits During Test Application,” IEEE Trans. CAD, IEEE vol. 17, no. 12, pp. 1325-1333, Dec. 1998. vol. Typical average power saving: 30-50% 50-60% with vector repetition (to satisfy peak power) ? ? ? With inserted vectors (to satisfy peak power) Copyright Agrawal, 2007 ELEC6270 Spring 09, Lecture 10 52 Traveling Salesperson Problem A. V. Aho, J. E. Hopcroft anf J. D. Ullman, Data A. Structures and Algorithms, Reading, Structures Reading, Massachusetts: Addison-Wesley, 1983. Massachusetts: E. Horowitz and S. Sahni, Fundamentals of E. Computer Algorithms, Computer Science Press, Computer Computer 1984. 1984. B. R. Hunt, R. L. Lipsman, J. M. Rosenberg, K. B. R. Coombes, J. E. Osborn and G. J. Stuck, A Guide to MATLAB for Beginners and Experienced Users, Cambridge University Experienced Cambridge Press, 2006. Press, ELEC6270 Spring 09, Lecture 10 53 Copyright Agrawal, 2007 Copyright ...
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This note was uploaded on 09/16/2011 for the course ELEC 7770 taught by Professor Agrawal,v during the Spring '08 term at Auburn University.

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