lec10_clock_constraints

lec10_clock_constraints - ELEC 7770 Advanced VLSI Design...

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: ELEC 7770 Advanced VLSI Design Spring 2010 A Linear Programming Solution to Clock Linear Constraint Problem Constraint Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University, Auburn, AL 36849 vagrawal@eng.auburn.edu http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr10/course.html Spring 2010, Mar 1 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 1 A General Sequential Circuit Inputs Combinational Logic Outputs Registers Clock Spring 2010, Mar 1 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 2 A Level-Sensitive Latch D QN Q CK Clock period, Tck CK Latch open Latch closed Latch open time Spring 2010, Mar 1 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 3 Alternative Implementation D Q CK J. Segura and C. F. Hawkins, CMOS Electronics, How It Works, How It Fails, Wiley Interscience, 2004, p.137. Spring 2010, Mar 1 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 4 Data Must be Stable Before Latch Closes 0→1→0→0→ D=0→1→1 0 1 delays 1 1→0→1→0→1→ QN CK = 1 → 1 → 0 1 0 1→1→0→0→ Clock period, Tck Q 0→0→1→0→1→ Unstable state CK Latch open Stable data Latch closed time Spring 2010, Mar 1 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 5 Data and Clock Parameters Clock period, Tck CK Latch open Latch closed Stable data D Setup time Hold time time time Q CK-to-Q delay Spring 2010, Mar 1 . . . Spring Stable Q time ELEC 7770: Advanced VLSI Design (Agrawal) 6 Design With Level-Sensitive Latches PI Level-sens. Latches PI Level-sens. Latches Comb. Logic Comb. Logic CK PO PO Spring 2010, Mar 1 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 7 Edge-Triggered Flip-flop D Master latch Slave latch Q QN CK Hold time CK Master open CK-to-Q Clock period, Tck Slave open Trigger edges 8 time Setup time Spring 2010, Mar 1 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) A Dynamic Implementation VDD CK D CK CK Q CK GND J. P. Uyemura, Chip Design for Submicron VLSI: CMOS Layout and Simulation, Thomsom, 2006, p. 229. Spring 2010, Mar 1 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 9 A Static Implementation VDD Q CK D CK CK CK GND J. P. Uyemura, Chip Design for Submicron VLSI: CMOS Layout and Simulation, Thomsom, 2006, p. 230. Spring 2010, Mar 1 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 10 Design With Edge-Triggered Flip-Flops Inputs Combinational Logic Outputs Flip-flops Clock Spring 2010, Mar 1 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 11 Setup Time Constraint Skew si FF i Note: All times for a FF should be adjusted by its clock skew. Combinational path delay δ(i,j) ≤ d(i,j) ≤ Δ(i,j) Travel time Tsi Thi Tqi Clock edge Constraint: i.e., si + Tqi + Δ(i,j) Δ(i,j) ≤ ≤ sj + Tck – Tsj Tck – Tsj – Tqi + sj – si Tck Skew sj FF j Tsj time Arrive no later than this This is known as long path constraint – prevents zero clocking Spring 2010, Mar 1 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 12 Hold Time Constraint Skew si FF i Note: All times for a FF should be adjusted by its clock skew. Combinational path delay δ(i,j) ≤ d(i,j) ≤ Δ(i,j) sj – si + Thj Tsi Thi Tqi Clock edge (si) Constraint: i.e., si + Tqi + δ(i,j) ≥ δ(i,j) ≥ sj + Thj Thj – Tqi + sj – si Tck Tsj time FF j Skew sj This is known as short path constraint – avoids double clocking Spring 2010, Mar 1 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 13 Solving Hold Time Problem (1) PI (FFi) PI PI (FFj) PO (FFj) PO PO (FFi) Fanout node External edges (variable delays) Spring 2010, Mar 1 . . . Spring Internal edges (fixed delays) 14 ELEC 7770: Advanced VLSI Design (Agrawal) Solving Hold Time Problem (2) Variables: Shortest arrival time at node i = ai Longest arrival time at node i = Ai Buffer delay on external edge (i,j) = wij Constants: At PI i: Ai = Λi and ai = λii, user specified. , user At At PI (FF) i: Ai = ai = Tqi At Spring 2010, Mar 1 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 15 Solving Hold Time Problem (3) Constraints: At PO i: Ai ≤ Rii and ai ≥ ri, user defined. At R At PO (FF) i: ai ≥ Thi, short path constraint. Ai ≤ Tck – Tsi, long path constraint. Optimization function (a linear approximation to Optimization minimum number of delay buffers): minimum minimize ∑ wij minimize wij all external edges (i,j) Spring 2010, Mar 1 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 16 Linear Programming Solution (1) minimize minimize Subject to: ∑ all external edges (i,j) Aj ≥ Ai + wij aj ≤ ai + wij Ai ≤ Ri ai ≥ ri Ai ≤ Tck – Tsi ai ≥ Thi Ai = Λi ai = λi Ai = Tqi ai = Tqi Spring 2010, Mar 1 . . . Spring wij wij for all i ε Fanin(j) for all i ε Fanin(j) for all i ε PO for all i ε PO for all i ε PO(FF i) for all i ε PO(FF i) for all i ε PI for all i ε PI for all i ε PI(FF i) for all i ε PI(FF i) 17 ELEC 7770: Advanced VLSI Design (Agrawal) Linear Programming Solution (2) Solution inserts smallest delays in interconnects Solution to satisfy short path constraints. to Maintains the specified clock period and Maintains satisfies setup time constraints. satisfies Reference: 1999. Spring 2010, Mar 1 . . . Spring N. Maheshwari and S. S. Sapatnekar, Timing Analysis and Optimization of Sequential Circuits, Springer, ELEC 7770: Advanced VLSI Design (Agrawal) 18 Shift Register Example 1 (Long Path) Shift F1 CK Δ F2 Δ F3 s1 Delay ≤ Δ s2 Delay ≤ Δ su ho s3 Zero skew t Ck-2-Q 2T Δ ≤ Delay su ho Ck-2-Q 0 su ho Ck-2-Q T Δ ≤ Delay su ho 0 s1 Ck-2-Q T su ho s2 Ck-2-Q 2T s3 su ho Ck-2-Q t Spring 2010, Mar 1 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 19 Shift Register Example 1 (Short Path) Shift F1 CK δ F2 δ F3 s1 s2 s3 Zero skew F1 su ho Ck-2-Q 0 su ho Ck-2-Q 0 Spring 2010, Mar 1 . . . su ho Ck-2-Q T su ho Ck-2-Q T su ho Ck-2-Q 2T su ho Ck-2-Q 2T t δ≥ Delay t Zero skew F2 20 ELEC 7770: Advanced VLSI Design (Agrawal) Shift Register Example 1 (Short Path) Shift F1 CK δ F2 δ F3 s1 s2 s3 F1 su ho 0 s1 Ck-2-Q su ho T δ≥ Delay T Ck-2-Q 2T su ho Ck-2-Q t F2 0 s2 su ho Ck-2-Q su ho 2T su ho Ck-2-Q 21 t Ck-2-Q Spring 2010, Mar 1 . . . ELEC 7770: Advanced VLSI Design (Agrawal) nonzero skew F2 Shift Register Example 2 (Short Path) Shift F1 δ F2 δ F3 CK su ho Ck-2-Q s1 F1 0 s2 su ho Ck-2-Q δ≥ Delay F2 su ho 0 s1 Ck-2-Q T su ho T s2 su ho 2T s3 t Ck-2-Q su ho 2T Ck-2-Q t Ck-2-Q Spring 2010, Mar 1 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 22 Shift Register Example 2 (Long Path) Shift F1 Δ F2 Δ F3 CK Zero skew su ho Ck-2-Q 2T Δ ≤ Delay su ho 2T s3 Ck-2-Q 23 s1 Delay ≤ Δ su ho Ck-2-Q 0 su ho Ck-2-Q T su ho 0 s1 s2 Delay ≤ Δ s3 t Δ ≤ Delay su ho T s2 t Ck-2-Q Ck-2-Q Spring 2010, Mar 1 . . . ELEC 7770: Advanced VLSI Design (Agrawal) ...
View Full Document

This note was uploaded on 09/16/2011 for the course ELEC 7770 taught by Professor Agrawal,v during the Spring '08 term at Auburn University.

Ask a homework question - tutors are online