lec11_zero_skew - ELEC 7770 Advanced VLSI Design Spring...

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Unformatted text preview: ELEC 7770 Advanced VLSI Design Spring 2010 Zero-Skew Clock Routing Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 vagrawal@eng.auburn.edu http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr10/course.html Spring 2010, Mar 5 Spring ELEC 7770: Advanced VLSI Design (Agrawal) 1 Zero-Skew Clock Routing FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF CK Spring 2010, Mar 5 Spring ELEC 7770: Advanced VLSI Design (Agrawal) 2 Zero-Skew: References H-Tree A. L. Fisher and H. T. Kung, “Synchronizing Large A. Systolic Arrays,” Proc. SPIE, vol. 341, pp. 44-52, Proc. vol. May 1982. May A. Kahng, J. Cong and G. Robins, “Hig-Performance A. Clock Routing Based on Recursive Geomrtric Matching,” Proc. Design Automation Conf., June Proc. ., 1991, pp. 322-327. 1991, M. A. B. Jackson, A. Srinivasan and E. S. Kuh, M. “Clock Routing for High-Performance IC’s,” Proc. Design Automation Conf., June 1990, pp. 573-579. Design Spring 2010, Mar 5 Spring ELEC 7770: Advanced VLSI Design (Agrawal) 3 Zero-Skew Routing Build clock tree bottom up: Leaf nodes are all equal loading flip-flops. Two zero-skew subtrees are joined to form a larger zero-skew Two subtree. subtree. Entire clock tree is built recursively. R.-S. Tsay, “An Exact Zero-Skew Clock Routing R.-S. Algorithm,” IEEE Trans. CAD, vol. 12, no. 2, pp. 242IEEE 249, Feb. 1993. J. Rubenstein, P. Penfield and M. A. Horowitz, “Signal J. Delay in RC Tree Networks,” IEEE Trans. CAD, vol. 2, IEEE vol. no. 3, pp. 202-211, July 1983. no. Spring 2010, Mar 5 Spring ELEC 7770: Advanced VLSI Design (Agrawal) 4 Balancing Subtrees (1) xL r1 c1/2 A c1/2 t1 C1 Subtree 1 Tapping point (1 – x)L r2 c2/2 B c2/2 t2 C2 Subtree 2 Spring 2010, Mar 5 Spring ELEC 7770: Advanced VLSI Design (Agrawal) 5 Balancing Subtrees (2) Subtrees 1 and 2 are each balanced (zero skew) trees, with delays t1 and t2 to respective skew) leaf nodes. leaf Total capacitances of subtrees are C1 and C2, Total respectively. respectively. Connect points A and B by a minimum-length Connect wire of length L. wire Determine a tapping point x such that wire Determine lengths xL and (1 – x)L produce zero skew. lengths Spring 2010, Mar 5 Spring ELEC 7770: Advanced VLSI Design (Agrawal) 6 Balancing Subtrees (3) Use Elmore delay formula: 0.69 r1(C1 + c1/2) + t1 = 0.69 r2(C2 + c2/2) + t2 Substitute: r1 = axL, r2 = a(1 – x)L c1 = bxL, c2 = b(1 –x)L abL2x + aL(C1+C2)x = 1.45 (t2 – t1) + aL(C1+C2)x aL(C2+bL/2) aL(C2+bL/2) Then solve for x: 1.45 (t2 – t1) + aL (C2 + bL/2) x = ─────────────────── aL(bL + C1 + C2) aL(bL Spring 2010, Mar 5 Spring ELEC 7770: Advanced VLSI Design (Agrawal) 7 Balancing Subtrees Example 1 Subtree parameters: Subtree 1: t1 = 5ps, C1 = 3pF Subtree 2: t2 = 10ps, C2 = 6pF Interconnect: L = 1mm Wire parameters: a = 100Ω/cm, b = 1pF/cm Tapping point: X= 1.45(t2 – t1) + aL (C2 + bL/2) 1.45(10–5) + 100×0.1(6 + 1×0.1/2) ────────────────── = ────────────────────── aL (bL + C1 + C2) 100×0.1(1×0.1+3+6) aL = 1.45(5 + 60.5)/(10×9.1) = 0.7445 1.45(5 Spring 2010, Mar 5 Spring ELEC 7770: Advanced VLSI Design (Agrawal) 8 Example 1 FF 0.77445mm t1 = 5ps, C1 = 3pF FF FF Subtree 1 FF To next level FF 0.2555mm t2 = 10ps, C2 = 6pF Subtree 2 Spring 2010, Mar 5 Spring ELEC 7770: Advanced VLSI Design (Agrawal) FF FF 9 Balancing Subtrees, x > 1 Tapping point set at root of tree with larger loading (C2, t2). Wire to the root of other tree is elongated to provide Wire additional delay. Wire length L is found as follows: additional Set x = 1 in abL2x + aL(C1+C2)x = 1.45(t2 – t1)+aL(C2+bL/2) Set abL i.e., L2 + (2C1/b)L – 2.9 (t2 – t1)/(ab) = 0 Wire length is given by: [(aC1)2 + 2.9 ab(t2 – t1)]½ – aC1 [(aC1) 2.9 L = ─────────────────── ──────────────────── ab R.-S. Tsay, “An Exact Zero-Skew Clock Routing Algorithm,” R.-S. IEEE Trans. CAD, vol. 12, no. 2, pp. 242-249, Feb. 1993. IEEE Spring 2010, Mar 5 Spring ELEC 7770: Advanced VLSI Design (Agrawal) 10 Balancing Subtrees Example 2 Subtree parameters: Subtree 1: t1 = 2ps, C1 = 1pF Subtree 2: t2 = 15ps, C2 = 10pF Interconnect: L = 1mm Wire parameters: a = 100Ω/cm, b = 1pF/cm Tapping point: 1.45(t2 – t1) + aL (C2 + bL/2) 1.45(t2 1.45(15–2) + 100×0.1(10 + ×0.1(10 1×0.1/2) 1×0.1/2) x = ─────────────────── = ────────────────────── aL (bL + C1 + C2) 100×0.1(1×0.1+1+10) aL = (18.85 + 100.5)/(10×11.1) = 1.0752 (18.85 Spring 2010, Mar 5 Spring ELEC 7770: Advanced VLSI Design (Agrawal) 11 Example 2, x = 1.0752 Setting x = 1.0, = = [(100×1)2 + 290 (15 – 2)]½ – 100×1 [(100 290 ─────────────────────── 100×1 100×1 = L [(aC1)2+2.9ab(t2 – t1)]½ – aC1 [(aC1) ──────────────────── ab 0.1735cm For a wire of 1.735mm length, place the clock feed at one end. Spring 2010, Mar 5 Spring ELEC 7770: Advanced VLSI Design (Agrawal) 12 Example 2, L = 1.735mm Example FF t1 = 2ps, C1 = 1pF L = 1.7355mm FF FF Subtree 1 FF To next level FF t2 = 15ps, C2 = 10pF Subtree 2 Spring 2010, Mar 5 Spring ELEC 7770: Advanced VLSI Design (Agrawal) FF FF 13 Balancing Subtrees, x < 0 Tapping point set at root of tree with smaller loading (C1, t1). Wire to the root of other tree is elongated to provide Wire additional delay. Wire length L found as follows: additional Set x = 0 in abL2x + aL(C1+C2)x = 1.45(t2 – t1)+aL(C2+bL/2) Set abL i.e., L2 + (2C2/b)L – 2.9 (t1 – t2)/(ab) = 0 Wire length is given by: [(aC2)2 + 2.9 ab(t1 – t2)]½ – aC2 [(aC2) 2.9 L = ──────────────────── ──────────────────── ab R.-S. Tsay, “An Exact Zero-Skew Clock Routing Algorithm,” R.-S. IEEE Trans. CAD, vol. 12, no. 2, pp. 242-249, Feb. 1993. IEEE Spring 2010, Mar 5 Spring ELEC 7770: Advanced VLSI Design (Agrawal) 14 Balancing Subtrees Example 3 Subtree parameters: x = Subtree 1: t1 = 15ps, C1 = 10pF Subtree 2: t2 = 2ps, C2 = 1pF Interconnect: L = 1mm Wire parameters: a = 100Ω/cm, b = 1pF/cm Tapping point: 1.45(t2 – t1) + aL (C2 + bL/2) 1.45(2–15) + 100×0.1(1 + 1×0.1/2) ─────────────────── = ────────────────────── aL (bL + C1 + C2) 100×0.1(1×0.1+1+10) aL = ( – 18.85 + 10.5)/(10×11.1) = – 0.0752 18.85 Spring 2010, Mar 5 Spring ELEC 7770: Advanced VLSI Design (Agrawal) 15 Example 3, x = – 0.0752 Setting x = 0.0, [(100×1)2+290 (15 – 2)]½ – 100×1 [(100 ─────────────────────── 100×1 100×1 = Spring 2010, Mar 5 Spring = = L [(aC2)2+2.9ab(t1 – t2)]½ – aC2 [(aC2) ────────────────── ab 0.1735cm ELEC 7770: Advanced VLSI Design (Agrawal) 16 Example 3, L = 1.255mm Example FF FF To next level t1 = 15ps, C1 = 10pF L = 1.735mm FF FF Subtree 1 FF t2 = 2ps, C2 = 1pF Subtree 2 Spring 2010, Mar 5 Spring ELEC 7770: Advanced VLSI Design (Agrawal) FF FF 17 Zero-Skew Design Delay =75ns Delay = 50ns Comb. Comb. FF A FF B FF C CK CK Tck = 75ns time Single-cycle path delay Spring 2010, Mar 5 Spring ELEC 7770: Advanced VLSI Design (Agrawal) 18 Nonzero-Skew Design Delay =75ns Delay = 50ns Comb. Comb. FF A FF B FF C CK Delay = 25ns CK Tck = 50ns time Single-cycle path delay Spring 2010, Mar 5 Spring ELEC 7770: Advanced VLSI Design (Agrawal) 19 Conclusion Zero-skew design is possible at the layout level. Zero-skew usually results in higher clock speed. Nonzero clock skews can improve the design Nonzero with reduced hardware and/or higher speed. with Spring 2010, Mar 5 Spring ELEC 7770: Advanced VLSI Design (Agrawal) 20 ...
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This note was uploaded on 09/16/2011 for the course ELEC 7770 taught by Professor Agrawal,v during the Spring '08 term at Auburn University.

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