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Unformatted text preview: ELEC 7770 Advanced VLSI Design Spring 2010 Gate Sizing
Vishwani D. Agrawal
James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 [email protected] http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr10
Spring 2010, Mar 10 Spring ELEC 7770: Advanced VLSI Design (Agrawal) 1 Clock Distribution Clock clock Spring 2010, Mar 10 ELEC 7770: Advanced VLSI Design (Agrawal) 2 Clock Power Clock
Pclk = CLVDD2f + CLVDD2f / λ + CLVDD2f / λ2 + . . .
stages – 1 = CLVDD2f
where CL = λ= Σ
n= 0 1 ─ λn total load capacitance constant fanout at each stage in distribution network Clock consumes about 40% of total processor power.
Spring 2010, Mar 10 ELEC 7770: Advanced VLSI Design (Agrawal) 3 Delay of a CMOS Gate Delay
Intrinsic capacitance Gate capacitance CMOS gate Cg Cint CL Propagation delay through the gate: tp = 0.69 Req(Cint + CL) ≈ 0.69 ReqCg(1 + CL /Cg) = tp0(1 + CL /Cg)
Spring 2010, Mar 10 ELEC 7770: Advanced VLSI Design (Agrawal) 4 Req, Cg, Cint, and Width Sizing and Width Req: equivalent resistance of “on” transistor, equivalent proportional to L/W; scales as 1/S, S = sizing /S, factor factor Cg: gate capacitance, proportional to CoxWL; gate scales as S scales Cint: iintrinsic output capacitance ≈ Cg, for ntrinsic for submicron processes submicron tp0: intrinsic delay = 0.69ReqCg; independent of sizing sizing
ELEC 7770: Advanced VLSI Design (Agrawal) 5 Spring 2010, Mar 10 Effective Fanout, f Effective fanout is defined as the ratio Effective
between the external load capacitance and the input capacitance: the f tp = = CL/Cg tp0(1 + f ) (1 Spring 2010, Mar 10 ELEC 7770: Advanced VLSI Design (Agrawal) 6 Sizing an Inverter Chain Sizing
1 2 N Cg1 Cg2 CL Cg2 tp 1 tp 2 = f2Cg1 = tp0 (1 + Cg2/Cg1) = tp0 (1 + Cg3/Cg2) N N = tp0 Σ (1 + Cgj+1/Cgj) j=1
7 tp
Spring 2010, Mar 10 = Σ tpj j=1 ELEC 7770: Advanced VLSI Design (Agrawal) Minimum Delay Sizing Minimum
Equate partial derivatives of tp with respect to Cgj to 0: 1/Cg1 – Cg3/Cg22 = 0, etc. or Cg22 = Cg1×Cg3, etc. i.e., gate capacitance is geometric mean of forward and backward gate capacitances. Also, Cg2/Cg1 = Cg3/Cg2, etc. i.e., all stages are sized up by the same factor f with respect to the preceding stage: CL/Cg1 = F = fN, tp = Ntp0(1 + F1/N)
Spring 2010, Mar 10 ELEC 7770: Advanced VLSI Design (Agrawal) 8 Minimum Delay Sizing Minimum
Equate partial derivatives of tp with respect to N to 0: dNtp0(1 + F1/N) ───────── = 0 dN i.e., F1/N – F1/N(ln F)/N = 0 or ln f = 1 → f = e = 2.7 and N = ln F Spring 2010, Mar 10 ELEC 7770: Advanced VLSI Design (Agrawal) 9 Sizing for Energy Minimization Sizing
Main idea: For a given circuit, reduce energy consumption by reducing the supply voltage. This will increase delay. Compensate the delay increase by transistor sizing. Ref: J. M. Rabaey, A. Chandrakasan and B. Nikolić, Digital Integrated Circuits, Second Edition, Upper Saddle River, New Jersey: Pearson Education, 2003, Section 5.4. Spring 2010, Mar 10 ELEC 7770: Advanced VLSI Design (Agrawal) 10 Summary Summary Device sizing combined with supply voltage Device reduction reduces energy consumption. reduction For large fanout energy reduction by a factor of For 10 is possible. 10 An exception is F = 1 case, where the minimum An size device is also the most effective one. size Oversizing the devices increases energy Oversizing consumption. consumption. Spring 2010, Mar 10 ELEC 7770: Advanced VLSI Design (Agrawal) 11 ...
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This note was uploaded on 09/16/2011 for the course ELEC 7770 taught by Professor Agrawal,v during the Spring '08 term at Auburn University.
 Spring '08
 Agrawal,V
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