lec14_LogicSyn - ELEC 7770 Advanced VLSI Design Spring 2010...

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Unformatted text preview: ELEC 7770 Advanced VLSI Design Spring 2010 Logic Synthesis Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 [email protected] http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr10 Spring 10, Apr 9 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 1 Logic Synthesis Logic Definition: To design a logic circuit such that it Definition: meets the specifications and can be economically manufactured: economically Performance – meets delay specification, or has Performance minimum delay. minimum Cost – uses minimum hardware, smallest chip Cost area, smallest number of gates or transistors. area, Power – meets power specification, or consumes Power minimum power. minimum Testablility – has no redundant (untestable) logic Testablility and is easily testable. and Spring 10, Apr 9 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 2 Synthesis Procedure Synthesis Minimization – Obtain MSOP or MPOS. This is Minimization also known as two-level minimization because the result can be implemented as a two-level AND-OR or NAND-NAND or NOR-NOR circuit. AND-OR Technology mapping – Considering design Technology requirements, transform the minimized form into one of the technologically realizable forms: one Spring 10, Apr 9 . . . Programmable logic array (PLA) Standard cell library Field programmable gate array (FPGA) Other . . . ELEC 7770: Advanced VLSI Design (Agrawal) 3 References on Synthesis References G. De Micheli, Synthesis and Optimization of G. Digital Circuits, New York: McGraw-Hill, 1994. Digital S. Devadas, A. Ghosh and K. Keutzer, Logic S. Synthesis, New York: McGraw-Hill, 1994. Synthesis Spring 10, Apr 9 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 4 Programmable Logic Array (PLA) Programmable A direct implementation of multi-output function direct as a two-level circuit in MOS technology. as PLA styles: NAND-NAND NOR-NOR Spring 10, Apr 9 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 5 Example: Two-Output Function Need four products: P1, P2, P3, P4 F1 0 1 4 5 12 13 A 8 9 F2 0 1 4 5 7 12 13 A 8 1 9 1 3 7 1 15 1 11 1 1 1 11 D C 3 2 15 D 1 C 1 2 6 14 1 10 1 6 14 1 10 1 B Spring 10, Apr 9 . . . ELEC 7770: Advanced VLSI Design (Agrawal) B 6 Two-Level AND-OR Implementation Two-Level Also known as technology-independent circuit. INPUTS C AND P1 F1 P2 A B P4 D Spring 10, Apr 9 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 7 OR P3 F2 NAND-NAND Implementation INPUTS C NAND NAND P1 F1 P2 A B P3 F2 D Spring 10, Apr 9 . . . P4 ELEC 7770: Advanced VLSI Design (Agrawal) 8 A NAND Gate in MOS Technology NAND VDD VDD VDD XY X Y X XY X XY Y Y GND GND GND R. C. Jaeger and T, N. Blalock, Microelectronic Circuit Design, Boston: McGraw-Hill, 2008, Section 6.8.2. Spring 10, Apr 9 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 9 A B NAND-NAND PLA NAND-NAND C D F1 F2 VDD VDD P1 P2 VDD VDD VDD VDD 10 P3 P4 GND Spring 10, Apr 9 . . . ELEC 7770: Advanced VLSI Design (Agrawal) NAND-NAND PLA SCHEMATIC NAND-NAND A INPUTS B C D F1 F2 OUTPUTS P1 P2 P3 P4 AND-plane Spring 10, Apr 9 . . . ELEC 7770: Advanced VLSI Design (Agrawal) OR-plane 11 Standard-Cell Design Standard-Cell Obtain two-level minimized form. Map the design onto predesigned building blocks called Map standard cells (technology mapping). standard Standard-cell library contains predesigned logic cells in Standard-cell the technology of manufacture. Examples of technology: the 90 nanometer CMOS 65 nanometer CMOS 45 nanometer CMOS ... This is known as application-specific integrated circuit This (ASIC). (ASIC). ELEC 7770: Advanced VLSI Design (Agrawal) 12 Spring 10, Apr 9 . . . Technology Mapping Technology Find a common logic elements, e.g., two-input Find NAND gate and inverter. NAND MSOP is converted into NAND-NAND circuit. Split gates into library cells, two-input NAND Split gates and inverters. gates Cover the circuit with standard cells, also split into Cover two-input NAND gates and inverters (graphtwo-input matching). Spring 10, Apr 9 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 13 A Typical Cell Library Typical Name Inverter NAND2 NAND3 NAND4 AOI21 OAI21 AOI22 XOR Area units (cost) 2 3 4 5 4 4 5 4 Inputs A A, B A, B, C A, B, C, D A, B, C A, B, C A, B, C, D A, B Output function, Z Z=A Z = AB Z = ABC Z = ABCD Z = AB + C Z = ( A + B)C Z = AB + CD Z = A B + AB 14 S. Devadas, A. Ghosh and K. Keutzer, Logic Synthesis, New York: McGraw-Hill 1994, Section 7.7, pp. 185-198. Spring 10, Apr 9 . . . ELEC 7770: Advanced VLSI Design (Agrawal) NAND3 Cell NAND3 Directed Acyclic Graph (DAG) (tree) Spring 10, Apr 9 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 15 NAND4 Cell NAND4 Spring 10, Apr 9 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 16 AOI21 Cell AOI21 Spring 10, Apr 9 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 17 OAI21 Cell OAI21 Spring 10, Apr 9 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 18 AOI22 Cell AOI22 Spring 10, Apr 9 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 19 XOR Cell XOR Spring 10, Apr 9 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 20 Technology Mapping Procedure Technology Obtain MSOP. Convert to two-level AND-OR circuit. Transform to two-level NAND-NAND circuit. Transform to two-input NAND and inverter tree Transform network. network. Perform an optimal pattern matching to obtain a Perform minimum cost tree covering. minimum Spring 10, Apr 9 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 21 Previous Example: 2-Level NAND INPUTS C NAND NAND P1 F1 P2 A B P3 F2 D Spring 10, Apr 9 . . . P4 ELEC 7770: Advanced VLSI Design (Agrawal) 22 Circuit is a Directed Acyclic Graph (DAG) (DAG) C P1 F1 A P2 P3 B F2 D Spring 10, Apr 9 . . . P4 ELEC 7770: Advanced VLSI Design (Agrawal) Each node is a NAND gate. 23 Splitting into a Forest of Trees Splitting C D B D C A B A D Spring 10, Apr 9 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 24 P2 P2 P2 F1 F2 Splitting DAG into Trees (Forest) Splitting C D C B D A B A D Spring 10, Apr 9 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 25 F1 P2 P2 P2 F2 A Simple Technology Mapping Simple NAND2 (3) C (2) NAND2 (3) F1 D B (2) NAND3 (4) P2 NAND3 (4) F2 NAND2 (3) A Cost = 24 NAND2 (3) Spring 10, Apr 9 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 26 Two-Input NAND Trees Two-Input C D B C D P2 F1 P2 P2 A B A D Spring 10, Apr 9 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 27 F2 Alternatively, in Graph Format Alternatively, C D B C D P2 F1 P2 P2 A B A D Spring 10, Apr 9 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 28 F2 An Improved Technology Mapping An C D Inverters inserted For pattern matching B OAI21 (4) (2) (2) P2 NAND3 (4) D F1 C P2 P2 A B A D Spring 10, Apr 9 . . . NAND3 (4) F2 (2) NAND2 (3) NAND2 (3) ELEC 7770: Advanced VLSI Design (Agrawal) Cost = 22 29 Alternatively, in Graph Format Alternatively, C (2) Nodes inserted For pattern matching OAI21 (4) D F1 P2 NAND3 (4) B C D P2 P2 A NAND2 (3) NAND3 (4) Cost = 22 F2 B A (2) Spring 10, Apr 9 . . . D NAND2 (3) ELEC 7770: Advanced VLSI Design (Agrawal) 30 Improved Technology Mapping Improved C (2) AOI21 (4) F1 D B (2) NAND3 (4) P2 NAND3 (4) F2 NAND2 (3) A Cost = 22 NAND2 (3) Spring 10, Apr 9 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 31 Original Reference Original K. Keutzer, “DAGON: Technology Binding and K. Local Optimization by DAG Matching,” Proc. Proc. 24th Design Automation Conf., 1987, pp. 3411987, 347. Spring 10, Apr 9 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 32 ...
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This note was uploaded on 09/16/2011 for the course ELEC 7770 taught by Professor Agrawal,v during the Spring '08 term at Auburn University.

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