lec16_PowerGround

lec16_PowerGround - ELEC 7770 Advanced VLSI Design Spring...

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Unformatted text preview: ELEC 7770 Advanced VLSI Design Spring 2010 Power and Ground Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 vagrawal@eng.auburn.edu http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr10 Spring 10, Apr 26 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 1 References References Q. K. Zhu, Power Distribution Network Design for VLSI, Hoboken, Q. Power Hoboken, New Jersey: Wiley, 2004. New M. Popovich, A. Mezhiba and E. G. Friedman, Power Distribution M. Networks with On-Chip Decoupling Capacitors, Springer, 2008. Networks C.-K. Koh, J. Jain and S. F. Cauley, “Synthesis of Clock and C.-K. Power/Ground Network,” Chapter 13, L.-T. Wang, Y.-W. Chang and K.-T. Cheng (Editors), Electronic Design Automation, MorganElectronic Kaufmann, 2009. pp. 751-850. J. Fu, Z. Luo, X. Hong, Y. Cai, S. X.-D. Tan, Z. Pan, “VLSI On-Chip VLSI Power/Ground Network Optimization Considering Decap Leakage Currents,” Proc. ASP-DAC, pp. 735-738, 2005. Proc. Decoupling Capacitors, Decoupling http://www.vlsichipdesign.com/index.php/Chip-Design-Articles/decouplinghttp://www.vlsichipdesign.com/index.php/Chip-Design-Articles/decoupling- Spring 10, Apr 26 . . . Spring ELEC 7770: Advanced VLSI Design (Agrawal) 2 Supply Voltage Supply 3.0 Supply voltage (V) 2.5 2.0 1.5 1.0 0.5 0.0 0.25 0.18 0.13 0.1 Minimum feature size (μm) Spring 10, Apr 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 3 Gate Oxide Thickness Gate Gate oxide thickness (A) 60 50 40 30 20 10 0 0.25 High gate leakage 0.18 0.13 0.1 Minimum feature size (μm) Spring 10, Apr 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 4 Power Supply Power V(t) Rg VDD Gate 1 R C Gate 2 5 + – R C Spring 10, Apr 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal) Switching Transients Switching Only Gate 1 switches (turns on): V(t) = VDD – Rg VDD exp[– t/{C(R+Rg)}]/(R+Rg) VDD VDD Rg/(R+Rg) V(t) 0 Spring 10, Apr 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal) time, t 6 Multiple Gates Switching Multiple Gate output voltage VDD 1 2 3 Number of gates switching many 0 time, t Spring 10, Apr 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 7 Decoupling Capacitor Decoupling A capacitor to isolate two electrical circuits. Illustration: An approximate model: VL(t) VDD = 1 + – Rg Rd Cd IL t=0 i(t) a t=0 t Spring 10, Apr 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 8 Approximate Load Current, IL Approximate 0, at, IL = a(2tp – t), 0, t < 2tp t > 2tp t<0 t < tp Spring 10, Apr 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 9 Transient Load Voltage Transient VL(t) = 1 – a Rg [ t – Cd Rg (1 – e – t/T) ], 0 < t < tp T = Cd (Rg + Rd) Spring 10, Apr 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 10 Realizing Decoupling Capacitor Realizing VDD VDD S B D OR S B D GND Spring 10, Apr 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal) GND 11 Capacitance Capacitance Cd = ≈ L γ ε Spring 10, Apr 26 . . . γ×WL×ε×ε0/Tox 0.26fF, for 70nm BSIM 38nm, 1.5462 4 ELEC 7770: Advanced VLSI Design (Agrawal) 12 = = = W = 200nm Leakage Resistance Leakage Igate = α × e – βTox ×W where α and β are technology parameters. where Rd = VL(t)/Igate Because V(t) is a function of time, Rd is Because difficult to estimate. The decoupling capacitance is simulated in spice. capacitance Spring 10, Apr 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 13 Power-Ground Layout Power-Ground Solder bump pads Vss Vss Vdd M5 Vdd/Vss supply Vdd/Vss equalization M4 Via Vdd Spring 10, Apr 26 . . . Vss Vdd 14 ELEC 7770: Advanced VLSI Design (Agrawal) Power Grid Power + – Spring 10, Apr 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 15 Nodal Analysis Nodal V2 g1 V1 Ci Vi g2 g3 V3 g4 Bi V4 Apply KCL to node i: 4 ∑ (Vk – Vi) gk – Ci ∂Vi/∂t = Bi k=1 Spring 10, Apr 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 16 Nodal Analysis Nodal G V – C V’ = B Where G is conductance matrix V is nodal voltage vector C is admittance matrix B is vector of currents V(t) is a function of time, V(0) = VDD B(t) is a function of time, B(0) ≈ 0 or leakage current Spring 10, Apr 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 17 Wire Width Considerations Wire Increase wire width to reduce resistance: Control voltage drop for given current Reduce resistive loss Reduce wire width to reduce wiring area. Minimum width restricted to avoid metal Minimum migration (reliability consideration). migration Spring 10, Apr 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 18 A Minimization Problem Minimization Minimize total metal area: A = n ∑ wi s i i=1 = n ∑ | ρ C i s i 2 | / xi i=1 Where n wi si ρ Ci xi = = = = = = number of branches in power network metal width of ith branch length of ith branch metal resistivity maximum current in ith branch voltage drop in ith branch Subject to several conditions. Spring 10, Apr 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 19 Condition 1: Voltage Drop Condition Voltage drop on path Pk: ∑ xi i ε Pk Where Δvk = ≤ Δv k maximum allowable voltage drop on kth path Spring 10, Apr 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 20 Condition 2: Minimum Width Condition Minimum width allowed by fabrication process: wi Where wi si ρ Ci xi W = ρ Ci s i / x i ≥ W = = = = = = metal width of ith branch length of ith branch metal resistivity maximum current in ith branch voltage drop in ith branch minimum line width Spring 10, Apr 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 21 Condition 3: Metal Migration Condition Do not exceed maximum current to wire-width ratio: Ci / wi Where wi si ρ Ci xi σi = x i / ( ρ s i) ≤ σi = = = = = = metal width of ith branch length of ith branch metal resistivity maximum current in ith branch voltage drop in ith branch maximum allowable current density across ith branch Spring 10, Apr 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 22 Decoupling Capacitance Decoupling Rg VDD + – Cd I(t) Spring 10, Apr 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 23 Decoupling Capacitance Decoupling Initial charge on Cd, Q0 = Cd VDD I(t): current waveform at a node T: duration of current Total charge supplied to load: T Q = ∫ I(t) dt 0 Spring 10, Apr 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 24 Decoupling Capacitance Decoupling Assume that charge is completely supplied by Cd. Remaining charge on Cd = Cd VDD – Q Voltage of supply node = VDD – Q/Cd For a maximum supply noise ΔVDDmax, For VDD – (VDD – Q/Cd) ≤ ΔVDDmax VDD Or Cd ≥ Q / ΔVDDmax Spring 10, Apr 26 . . . ELEC 7770: Advanced VLSI Design (Agrawal) 25 ...
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