lec17_Crosstalk - ELEC 7770 Advanced VLSI Design Spring...

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Unformatted text preview: ELEC 7770 Advanced VLSI Design Spring 2010 Interconnects and Crosstalk Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 vagrawal@eng.auburn.edu http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr10 Spring 10, May 4 Spring ELEC 7770: Advanced VLSI Design (Agrawal) 1 Crosstalk Crosstalk Signal noise due to coupling between Signal interconnects. interconnects. Victim – affected interconnect; Aggressor(s) – Victim noise causing interconnect(s). noise Principal cause – capacitive coupling in long Principal parallel wires. parallel Transients behavior. Simulation for functional verification. Avoidance by physical design, perpendicular Avoidance wires, shielding. wires, Spring 10, May 4 ELEC 7770: Advanced VLSI Design (Agrawal) 2 Victim and Aggressors Victim Ceff = Cg + 2C0 1 V 0→VDD 0V C0 Spring 10, May 4 2 Cg 0V C0 ELEC 7770: Advanced VLSI Design (Agrawal) 3 Victim and Aggressors Victim Ceff = Cg 1 V 0→VDD 0→VDD C0 Spring 10, May 4 2 Cg 0→VDD C0 ELEC 7770: Advanced VLSI Design (Agrawal) 4 Victim and Aggressors Victim Ceff = Cg + 4C0 1 V 0→VDD VDD→0 C0 Spring 10, May 4 2 Cg VDD→0 C0 ELEC 7770: Advanced VLSI Design (Agrawal) 5 Crosstalk Induced Capacitance Crosstalk Victim Neighbor 1 Neighbor 2 Ceff ↑ ↑ ↑ Cg ↑ ↑ ↓ Cg + 2C0 ↑ ↓ ↑ Cg + 2C0 ↑ ↓ ↓ Cg + 4C0 ↓ ↑ ↑ Cg + 4C0 ↓ ↑ ↓ Cg + 2C0 ↓ ↓ ↑ Cg + 2C0 ↓ ↓ ↓ Cg Spring 10, May 4 ELEC 7770: Advanced VLSI Design (Agrawal) 6 Example Example Time t < 0 Victim at VDD, both neighbors at VDD Charge on victim = Cg VDD Time t = 0 Both neighbors switch, VDD → 0 Victim’s effective capacitance, Cg + 4C0 4C Victim’s voltage = Cg VDD/(Cg + 4C0) < VDD 4C Time t > 0 Victim charges to VDD Spring 10, May 4 ELEC 7770: Advanced VLSI Design (Agrawal) 7 Example (Cont.) Example Victim’s voltage VDD Cg VDD/(Cg + 4C0) 0 Time, t Spring 10, May 4 ELEC 7770: Advanced VLSI Design (Agrawal) 8 Reducing Crosstalk Reducing GND Spring 10, May 4 1 VDD ELEC 7770: Advanced VLSI Design (Agrawal) 2 GND 9 References References J. E. Ayers, Digital Integrated Circuits Analysis J. and Design, Second Edition, Boca Raton: CRC and Boca Press, 2010, Chapter 7. Press, X. Chen and N. A. Touba, “Fundamentals of X. CMOS Design,” Chapter 2, L.-T. Wang, Y.-W. Chang and K.-T. Cheng (Editors), Electronic Design Automation, Morgan-Kaufmann, 2009. Design Morgan-Kaufmann, pp. 39-95. pp. H. Grabinski, Interconnects in VLSI Design, H. Springer, 2000. Springer, Spring 10, May 4 ELEC 7770: Advanced VLSI Design (Agrawal) 10 ...
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This note was uploaded on 09/16/2011 for the course ELEC 7770 taught by Professor Agrawal,v during the Spring '08 term at Auburn University.

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