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Murali_Advanced VLSI Report

Murali_Advanced VLSI Report - 1 Study of operation of Flip...

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1 Abstract This project examines the operations of a flip flop in the subthreshold region. Subthreshold operation is emerging as a good technique for low power design of circuits where speed of execution is not a primary concern. In this project, I aim to find the minimum energy point of a flip flop, and compare my results with the result obtained in [3]. The flip flop designed for this project is a master-slave D flip flop. The flip flop was designed in Design Architect, and the netlist was modified to 90nm technology. The simulation was done using HSPICE. Results show that the flip flop operates perfectly in the subthreshold region of 90nm technology while providing reasonable power and energy savings. Index Terms master-slave flip flop, low voltage operation, very low power design, subthreshold operation. I. I NTRODUCTION H ERE IS a growing concern with the increase in power dissipation with the scaling down of transistors. We know that Total Power (P total ) dissipated in a transistor consists of Static Power (P static ) and Dynamic Power (P dynamic ). While the scaling down of transistors causes a reduction in dynamic power due to faster switching of the circuit, there is an increase in leakage current flowing through the circuit due to scaling down of the threshold voltages hence causing a significant increase in static power dissipation. Hence, there is a significant interest in developing techniques for more power and energy efficient circuits at high leakage technologies. One of the possible solutions for this conundrum is subthreshold voltage operation of circuits. For circuit operations where execution speed is not the primary motive, the circuits can be operated at voltage below the threshold voltages of the transistors making up the circuit without losing the functionality of the circuit. We find that scaling down the voltage gradually reduces short circuit power dissipation and it is completely eliminated at V dd ≤ |V tp | + V tn . Manuscript received May 3, 2010. This work was supported by Dr. Vishwani D. Agrawal and the ECE department at Auburn University. Murali Dharan is a Graduate Student of Electrical and Computer Engineering at Auburn University, Auburn, AL 36849 USA (e-mail: [email protected]). Dr. Vishwani D. Agrawal is a James J. Danaher Professor at Auburn University, Auburn AL 36849 USA. He is with the Department of Electrical and Computer Engineering. ([email protected]).
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