Prardiva_finalreportvlsi - Verification of Elmore Delay...

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                    Verification of Elmore Delay Formula: Prardiva Mangilipally I. INTRODUCTION Delay calculation is the term used in integrated circuit design for the calculation of the gate delay of a single logic gate and the wires attached to it. Static timing analysis computes the delays of entire paths, using delay calculation to determine the delay of each gate and wire. There are many methods used for delay calculation for the gate itself. The choice depends primarily on the speed and accuracy required.Circuit simulators such as SPICE may be used. This is the most accurate, but slowest, method. Two dimensional tables are commonly used in applications such as logic synthesis, placement and routing. These tables take an output load and input slope, and generate a circuit delay and output slope. A very simple model called the K-factor model is sometimes used. This approximates the delay as a constant plus k times the load capacitance. A more complex model called Delay Calculation Language, or DCL, calls a user-defined program whenever a delay value is required. This allows arbitrarily complex models to be represented, but raises significant software engineering issues. Logical effort provides a simple delay calculation that accounts for gate sizing and is analytically tractable. II. INTERCONNECT DELAY MODELING Delays on signals due to wires is significant. Modern designs must meet timing specifications which the layout tools must guarantee. This timing issue is taken care by making the layout area small, making the clusters close together, making the wires shorter. All these methods do not guarantee that the timing specifications are met. In order to accurately predict the interconnect delay, delay is modeled. there are many ways to calculate the delay of a wire. The delay of a wire will normally be different to each destination. Model 1: Delay=finite speed signal propagation through physical wires. Here delay is considered to be proportional to length. This model is really easy but not quantitatively accurate. Model 2: This is a wire load model is which the delay is considered to be affected by circuit drive limitations. Wire load modeling allows you to estimate the effect of wire length and fan-out on the resistance, capacitance, and area of nets. Design
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This note was uploaded on 09/16/2011 for the course ELEC 7770 taught by Professor Agrawal,v during the Spring '08 term at Auburn University.

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Prardiva_finalreportvlsi - Verification of Elmore Delay...

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