Praveen Venkataramani_Project

Praveen Venkataramani_Project - 1 Design of Clock...

Info iconThis preview shows pages 1–2. Sign up to view the full content.

View Full Document Right Arrow Icon
Abstract —Clocks distribution networks are important part of synchronous circuits to ensure the availability of the clock signal at each flip flops across the integrated circuit. There are several design methodologies proposed to design effective clock distribution networks. However, the exponential reduction in feature size of the transistors that necessitates high speed clock signals only create more difficulties in practically designing an efficient clock distribution network. This report discusses the various clock distribution used in conventional sequential circuits and some of the emerging designs. Index Terms —Clock distribution networks, clock skew, De- skew buffers, H-trees, wireless clock distribution. I. INTRODUCTION Clock signals are important in synchronous circuits to synchronize different data signals arriving from different parts of the integrated circuit, such that the correct data is available for computation. Due to impedances present in interconnects there are mismatches in the clock arrival time due to spatial distances between two clocks. These mismatches in time are known as clock skews. Due noises caused by other interconnect lines running in parallel with the clock signals, clock signals arriving at two different registers with the same clock input experience a phase noise, commonly known as clock jitter [1]. Clock distribution networks ensure that these constraints regarding clock skew and jitters are minimized. Design of clock distribution network is however a cumbersome task and a designer must decide the clock distribution before the circuit is designed because the difficulty in designing an efficient clock distribution network increases in the latter stages of design [1]. Different techniques such as H-tree, buffered clock trees and meshed clock network are used in the design of the clock networks. Since the interconnects do not scale proportionally to the rapidly scaling transistor feature sizes that operate at high clock frequencies, sets a difficulty in designing an efficient clock distribution networks. The paper is organized as follows. Section II discusses the clock constraints and the various clock distribution techniques used. Section III discusses about the various researches for future clock distribution networks. . Figure 1 Clock Skews [2] II.C LOCK R EQUIREMENTS AND TYPES OF C LOCK DISTRIBUTION NETWORKS A. Clock Requirements Due to various delay mismatches due to clock interconnect resistances and delay in the combinational circuits between sequential elements; it is important to set a definite clock transition period to ensure proper latching of the data at the flip flops. Problems arising due to incorrect clock period include race conditions that produce incorrect output at the
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 2
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 09/16/2011 for the course ELEC 7770 taught by Professor Agrawal,v during the Spring '08 term at Auburn University.

Page1 / 3

Praveen Venkataramani_Project - 1 Design of Clock...

This preview shows document pages 1 - 2. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online