SPS Final Project

SPS Final Project - 1 Timing Simulation of 45 nm Technology...

Info iconThis preview shows pages 1–3. Sign up to view the full content.

View Full Document Right Arrow Icon
1 Abstract —A timing simulation is presented for a MOSFET implemented inverter and 2-input NAND gate in a 45 nm technology. Gate tunneling currents are characterized for technology nodes less than 180 nm and the temperature dependence of this leakage is discussed. I. INTRODUCTION ORWARD progression in the MOS/VLSI industry is driven by the demand for faster circuit speed. An increase in MOSFET operating speed is often accomplished by decreasing channel length. As a result, the gate oxide thickness is often decreased proportionally as well. Two topics will be discussed in this paper. First, the delay of both an inverter and 2-input NAND gate for the 45 nm technology node will be presented. Second, the effects of leakage current due to gate tunneling currents as gate thickness is scaled down is examined. The temperature dependence of gate tunneling currents is also discussed. When the gate SiO 2 thickness is less than 2 nm the effects of carrier tunneling through the oxide begin to degrade the performance of the transistor [1]. The International Technology Roadmap for Semiconductors (ITRS) specifies the maximum allowed gate leakage current density (J limit ) for high- performance CMOS logic chips to be 188 A/cm 2 for 90 nm technology [2]. J limit is defined at 300K. It can be seen that this limit is reached when the gate oxide thickness (t ox ) is scaled down to 1.5 nm [3]. Due to the demand of devices with a gate oxide thickness at or below 1.5 nm, the effects of temperature variation on gate tunneling current should be studied more thoroughly. In this paper a nMOSFET will be considered. II. TIMING ANALYSIS OF 45 NM TECHNOLOGY A. FreePDK45 Library The models (NMOS_VTL and PMOS_VTL) provided in the free open-source 45 nm library, FreePDK45, developed by NCSU were used in simulation of the inverter and the 2-input NAND gate. LTSpice was used to run the netlist file. The rise and fall time of all input stimuli were set to 1 ns and the supply voltage was set to 1.2 V. B. MOSFET Inverter For the simulation of the inverter the input alternates between VDD and ground at a frequency of 10 MHz. When the input to the inverter, Vin, changes from low to high, the output of the inverter, Vout, takes 7 ns to fall to a steady state value. However, when Vin changes from high to low, Vout takes 45 ns to rise to a steady state value. The netlist shown in Fig. 1 was used to generate the plot shown in Fig. 2. *Main inverter netlist .param supply=1.2 .include '180nm.lib' .global Vdd Gnd Vdd Vdd Gnd 'supply' .include NMOS_VTL.inc .include PMOS_VTL.inc .tran 0 115ns 0 0.1ns M1 Out In Gnd Gnd NMOS_VTL M2 Out In Vdd Vdd PMOS_VTL V1 In Gnd pulse(0 'supply' 10n 1n 1n 50n 100n) .END Fig. 1. Netlist for inverter Fig. 2. Plot of Vin and Vout of inverter Timing Simulation of 45 nm Technology and Analysis of Gate Tunneling Currents in 90, 65, 45, and 32 nm Technologies Steven P. Surgnier F
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
2 C. 2-input NAND Gate For the simulation of the 2-input NAND gate, input A alternates from high to low at a frequency of 2 MHz while
Background image of page 2
Image of page 3
This is the end of the preview. Sign up to access the rest of the document.

Page1 / 5

SPS Final Project - 1 Timing Simulation of 45 nm Technology...

This preview shows document pages 1 - 3. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online