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Unformatted text preview: Test Pattern Generator for Built-in Self-Test using Spectral Methods Alok S. Doshi and Anand S. Mudlapur Auburn University 200 Dept. of Electrical and Computer Engineering, Auburn, AL, USA doshias,firstname.lastname@example.org Abstract A new method for test pattern generation (TPG) in a built-in self-test (BIST) environment is proposed here. The TPG uses the characteristic information of the circuit to generate the test vectors internally. The characteristic information of the circuit is ex- tracted using known spectral methods. The algorithm was tested on different counter circuits and performs exceptionally well compared to the random test pat- terns by ATALANTA . The hardware required for the TPG in the counter circuit is the same irrespec- tive of the size of the counter. Thus the area overhead is minimal for greater length counter circuits. 1 Introduction As the technology improves by the day, the logic- to-pin ratio on the chip increases proportionally . This makes it difficult to analyze the signals on the device. Also the test application time associated with external testers reaches an upper bound in large cir- cuits. At speed testing using an external ATE (Au- tomatic Test Equipment) is extremely expensive and prohibitive amounts of test data must be stored in the ATE. BIST has been emerging as the single most effective solution to the above mentioned problems. BIST is an on-chip testing system that generates test vectors to detect faults and verifies whether the hard- ware is performing correctly. The main components of a BIST system are a TPG that applies a sequence of patterns to the circuit under test (CUT), a re- sponse compacter that compacts the responses into a signature, and a signature comparator that compares the signature to a fault free signature value. Testing using pseudo-random test patterns often results in large test sets or insufficient fault cover- ages. Due to the low hardware costs BIST based on random patterns is very attractive. Linear Feed- back Shift Registers (LFSRs) are commonly used in pseudo-random test pattern generators in BIST schemes. Pseudo-random sequences are useless for random-pattern-resistant faults . A common so- lution to random-pattern-resistant faults is using weighted random patterns, which are found to yield better fault coverages . While generating weighted random patterns the probability of obtaining a 0 or 1 at a particular input is biased toward detecting random-resistant faults. But this reasoning collapses since no one set of weight may be suitable for all faults. Deterministic BIST techniques such as stored pattern testing involve the application of specific test vectors, each providing an increase in fault coverage....
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- Spring '08