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Unformatted text preview: ELEC 6970 Low power design Project Report Yijing Chen Insert delays to eliminate glitches 1. Introduce array multiplier : The array multiplier offers lower speed but consume smaller areas than Wallace-tree multiplier. As shown array multiplier in Fig. 1, multiplicand bits are simultaneously input to all the partial product generators at every stage. All full adders start computing at the same time without waiting for the propagation of sum and carry signals from the previous stage. The outputs of the multiplier have many glitches. As for the power dissipation, the signal transition activity directly influences the dynamic power dissipation. This results in spurious transitions at the output and wastes power. Furthermore, as shown in Fig. 2, since these spurious transitions are propagated to the next stage continuously, their numbers grow stage by stage like a snow ball. This causes a significant increase in power dissipation. A0 A1 A2 A3 B3 B2 B1 B0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Full adder B A Carry in Sum output Sum input Carry out Array Cell A0 A1 A2 A3 B3 B2 B1 B0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Full adder B A Carry in Sum output Sum input Carry out Full adder B A Carry in Sum output Sum input Carry out Array Cell Figure 1. Traditional 4x4 multiplier Figure 2. spurious transition in multiplier 2. Delay balancing array multiplier To solve the glitch problem, for simplicity, we assume a unit delay model where the delay...
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This note was uploaded on 09/17/2011 for the course ELEC 6970 taught by Professor Staff during the Spring '08 term at Auburn University.
- Spring '08