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PROJECT REPORT
ON
Effect of Variation of threshold voltage on power consumption,
delay and area of a 32x32 bit array Multiplier
FOR
ELEC 6970: Low Power Design
Sachin Dhingra
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G
I
D
I
sub
I
PT
I
GIDL
n+
n+
Ground
V
DD
R
Objective:
To reduce the leakage current by varying the threshold voltage of the transistors and observe its effect
on the overall power consumption, delay and area of the circuit
Background:
This section gives a brief description of the concepts required for understanding the project.
Threshold Voltage:
It is the minimum voltage required to turn on a transistor.
Threshold voltage is given by:
V
t
=
V
t0
+ γ[(Φ
s
+
V
sb
)½ Φ
s
½]
Where,
V
t0
– Threshold voltage when source is at body potential (i.e.
V
sb
= 0 V
)
γ
– Body effect parameter, a function of doping level, permittivity and oxide thickness
Φ
s
–
Surface potential, a function of thermal voltage and doping level
V
sb
– Source to Body voltage
So, Threshold Voltage is a function of Doping concentration, Thickness of oxide and
Source to Body Voltage (Body bias voltage).
Leakage Power:
CMOS circuits mostly consume power only during transitions; the power consumed by
CMOS circuits during steady state is known as Static power also known as Leakage power. One of the biggest
contributors of the leakage power is the subthreshold conduction of a
transistor.
The leakage current is given by
…..1
Where,
V
t
– Threshold voltage
I
0
– I
ds
@ cutoff i.e. V
gs
= V
t
n – experimentally derived constant
Delay:
The switching time of a transistor decides the delay of a gate. Delay is inversely proportional to the
threshold voltage of a transistor.
……2
α ~1, for short channel devices
Critical Path:
It is the path in the circuit which has the longest delay from the input to the output.
From 1 and 2 we deduce that the Delay of a circuit increases as the threshold voltage increases and the leakage
power reduces.
Multiplier design:
The multiplier was design using VHDL. Following is the generate statement which creates a multiplier using
cells as a component.
gen1: for i in 1 to n generate
gen2: for j in 1 to n generate
cond0: if ( (j=1)and(i<n) ) generate
cel: cell port map( A(i),B(j),si((i1)*n+j),ci((i1)*n+j),Y(i),ci((i1)*n+j+1) );
end generate;
cond1: if ( (j>1)and(j<n)and(i<n) ) generate
cel: cell port map( A(i),B(j),si((i1)*n+j),ci((i1)*n+j),si(i*n+j1),ci((i1)*n+j+1) );
end generate;
)
1
(
gs
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This note was uploaded on 09/17/2011 for the course ELEC 6970 taught by Professor Staff during the Spring '08 term at Auburn University.
 Spring '08
 Staff
 Frequency, Volt

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