Dhingra_ThresholdVoltage

Dhingra_ThresholdVoltage - Effect of Variation of threshold...

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Unformatted text preview: Effect of Variation of threshold voltage on power consumption, delay and area of a 32x32 bit array Multiplier ELEC 6970: Low Power Design Class Project By: Sachin Dhingra 09/17/11 ELEC 6970: Low Power Design 2 Outline Introduction Design of the multiplier Background Leakage Power Threshold Voltage Results Conclusion Future Work 09/17/11 ELEC 6970: Low Power Design 3 Introduction Design and Verification of an array multiplier using VHDL Reduction of leakage current of the circuit by variation of the threshold voltage (V t ) Sub-threshold conduction current decreases as the V t increases Increase in V t also leads to higher switching delays Aim: To reduce the leakage current by varying the threshold voltage of the transistors and observe its effect on the overall power consumption, delay and area 09/17/11 ELEC 6970: Low Power Design 4 Leakage Power Leakage Power components Sub-threshold Leakage current Reverse bias p-n junction conduction Gate induced drain leakage Drain source punch through (Short channel effects) Gate tunneling Sub-threshold Leakage current Carrier diffusion between the source and the drain region of the transistor Grows exponentially as V t decreases ) 1 ( gs...
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Dhingra_ThresholdVoltage - Effect of Variation of threshold...

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