exam1.sol - ELEC 5970-001/6970-001 Special Topics in...

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ELEC 5970-001/6970-001 Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits Fall 2005 Exam 1 Assigned 10/18/05, due 10/25/05 Attempt all three problems. Total points 30 Problem 1: Determine the activity factor α, the average probability of transitions per clock per gate output, for a four NAND gate exclusive-OR circuit. Assume that all gates have delays proportional to their fanout, the output gate has a fanout of 1, and all primary input vectors are equally likely. How will the activity factor change if 00 input pattern did not occur and the other three patterns occurred with equal probability. Use event-driven simulation for this problem. Solution: ELEC5970/6970 Exam 1 Solution Page 1 of 6 Fall 2005 Delay = 2 Delay = 1 Delay = 1 Delay = 1 A B C D E F 00 10 11 01 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 start 1 Circuit schematic Input state transition graph (STG).
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The above input state transition graph (STG) has 16 state transitions. If all vectors occur with equal probability, then for each vector the next vector can be any of the four vectors (including itself). A minimal length input vector sequence that traverses each arc exactly once is the following Euler tour: Vector number PI Vector (A, B) State transition in STG 1 00 Initial state 2 00 1 3 11 2 4 10 3 5 10 4 6 01 5 7 10 6 8 11 7 9 00 8 10 11 9 11 01 10 12 01 11 13 00 12 14 01 13 15 11 14 16 10 15 17 00 16 The following table shows the event-driven simulation of the above 17 vectors, starting all four gates in the unknown state. Since the critical path delay is 4 units, a vector period of 5 units is used. Gate transitions are shown in boldface. PI vector (A, B) Time stack Event list Signal values Activity list A B C D E F 00 0 A, X →0 B, X →0 0 0 X X X X C, D, E 1 D, X →1 E, X →1 0 0 X 1 1 X F 2 C, X 1 F, X →0 0 0 1 1 1 0 D, E 3 0 0 1 1 1 0 4 0 0 1 1 1 0
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exam1.sol - ELEC 5970-001/6970-001 Special Topics in...

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