ELEC 5270/ELEC 6270 LowPower Design of Electronic Circuits
Final Exam, May 4, 2011
Total 25 points
Broun 102, 4:006:30PM
Instructions: Please read all problems before writing your answers. Attempt all six (6)
problems. Be sure to revise your answers before turning them in. Please number your
answer sheets, and on the first page identify the test as shown above, write your name
and the total number of pages, and staple them before submitting. Thank you.
Problem 1:
5 points
Using the Elmore delay formula, show that the delay of a long interconnect of length s
with distributed resistance r ohms per unit length and capacitance c farads per unit length
is half of the delay of a lumped resistance of rs ohms feeding a lumped capacitive load of
cs farads.
Solution:
To use the Elmore delay formula, we model the distributed interconnect as a
cascade of n sections of length s/n each having resistance rs/n and capacitance cs/n,
where r and c are the per unit length resistance and capacitance of the interconnect. See
the following schematic.
From Elmore delay formula, the delay from source to node n is:
Τ
= 0.69[R1C1 + (R1+R2)C2 + . . . + (R1+R2+ . . . +Rn)Cn]
= 0/69[(rc + 2rc + 3rc + . . . + nrc)(s/n)
2
]
= 0.69[rc[n(n+1)/2](s/n)
2
] = 0.69 rcs
2
(n+1)/(2n)
→
0.69rcs
2
/2 as n
→
∞
ELEC5270001/6270001, Spring 2011, Final Exam Problems and Solutions
1 of 8
R1=rs/n
C1=cs/n
1
R2=rs/n
C2=cs/n
2
Rn=rs/n
Cn=cs/n
n
source
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View Full DocumentA lumped interconnect is shown below.
For a lumped RC interconnect, where R = rs and C = cs, the current in the circuit is:
I(t)
= Ve
– t/RC
/R, where V is the source voltage applied at time t = 0
Voltage across the load capacitance is whose initial voltage was v(0) = 0,
v(t)
= V – I(t)R = V(1 – e
1 – t/RC
)
Delay T’ is the time for the output voltage to attain a value 0.5V. Therefore
T’
= 0.69RC = 0.69rcs
2
, which is twice that of the distributed delay T
Problem 2:
5 points
Briefly answer the following questions about the operation of a static RAM:
(a) What are the voltages bit and bitbar lines are raised to during the precharge phase
of operation?
(b) Why does the power consumed in reading a memory cell increase as the number
of memory cells in the SRAM increase?
(c) What effect does pulsing of wordline during read operation has on precharge
power?
(d) How does the sense amplifier save power consumption in SRAM?
(e) The sleep and powerdown modes save static power consumption during the
periods when a SRAM block is not required to perform the read/write functions.
What is the difference between these two modes.
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 Energy, Frequency, Volt, Watt, FINAL EXAM PROBLEMS

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