This preview shows pages 1–2. Sign up to view the full content.
This preview has intentionally blurred sections. Sign up to view the full version.View Full Document
Unformatted text preview: Glitch filtering in gate-level switching power estimation using Dual-transition probability 1 st Author 1st author's affiliation 1st line of address 2nd line of address Telephone number, incl. country code 1st author's email address 2nd Author 2nd author's affiliation 1st line of address 2nd line of address Telephone number, incl. country code 2nd E-mail ABSTRACT Most of existing gate-level probabilistic approaches on power estimation fails to model glitch filtering effect accurately. However, this effect could have significant impact on the power dissipation in a circuit and therefore not negligible. In this paper, we propose an accurate glitch filtering method which can be applied to existing probability simulation and tagged probability simulation techniques. Our glitch filtering method is based the new measure of dual-transition probability that captures the probability of states on one node at two different time instance. Experiments show that the application to the tagged probability simulation gives a power estimation which has a more stable performance than that of the original one. For certain circuits with a large component of glitch power, up to 28% estimation accuracy improvements have been obtained. Keywords Dual-transition probability, dual-transition correlation coefficient 1. INTRODUCTION Power estimation refers to the techniques that can estimate or predict the average power and maximum power for a given circuit. Its been well understood that accurate power estimation methods are critical to IC designs because the power consumptions for each module must meet the specification during the design phase. Otherwise, a costly redesign process is inevitable. Numerous computer aided design tools for power estimation has been developed to address this issue. From the interest of estimation and circuit details provided, power estimation techniques ranges from circuit level SPICE simulation to high level estimation of power dissipation of a CPU. For gate level power estimation, a gate level netlist of the circuit is provided. The power components that consist of the total power dissipation for a CMOS circuit are switching power ( switching P , caused by the signal transitions charging and discharging load capacitors), leakage power ( leakage P , caused by sub-threshold current of transistors when no input changes) and short-circuit power ( short circuit P- , power dissipation during the gate switching, when both PMOS and NMOS network are turned on) 7. Among these three components, switching power has been the dominant component in the past decades. 2 switching L dd clk P kC V f = , where k is the switching activity factor, L C is the load capacitance, dd V is the supply voltage and clk f is the clock frequency. Although leakage power is becoming more and more significant as the device size keeps shrinking, an accurate estimation of switching power is always of great interests....
View Full Document