ELEC 5270001/6270001 LowPower Design of Electronic Circuits
Spring 2011
Homework 1 Problems
Assigned 2/21/11, due 2/28/11
Problem 1:
A 32 bit bus operates at 1.0V and 2GHz clock rate. Each bit wire, driven by
a CMOS buffer, has a total capacitance of 2pF. Each wire has a toggling probability of
0.75 per clock cycle. What is the total dynamic power dissipation of the bus drivers? Will
the inversion encoding scheme reduce the power consumption?
Problem 2:
A clock driver has a total output capacitance of 50pF. The supply voltage is
0.9V and the clock frequency is 2GHz. Calculate the power consumption of the clock
signal.
Problem 3:
Prove that a CMOS gate consumes no shortcircuit power when V
DD
≤ V
tn
+ 
V
tp
, i.e., supply voltage is below the sum of the threshold voltage magnitudes for the n
and p channel MOSFETs.
Problem 4:
Using the Elmore delay formula, show that the delay of a long interconnect
of length s is proportional to s
2
. Suppose, to reduce the delay of the interconnect we split
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This note was uploaded on 09/17/2011 for the course ELEC 6970 taught by Professor Staff during the Spring '08 term at Auburn University.
 Spring '08
 Staff
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