hw2prob - ELEC 5270-001/6270-001 Low-Power Design of...

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ELEC 5270-001/6270-001 Low-Power Design of Electronic Circuits Spring 2011 Homework 2 Problems Assigned 3/7/11, due 3/21/11 Problem 1: (a) In a CMOS technology all pMOS and nMOS transistors are designed to have identical “off” resistance of 10M Ω . In comparison, their “on” resistances are negligible. For a supply voltage of 1 volt, find the leakage current of a two-input NAND gate as a function of its input logic states. (b) Construct a 2-to-1 multiplexer using four two-input NAND gates. Tabulate all input vectors and their leakage currents. Identify a minimum leakage vector (MLV) and a maximum leakage vector and specify their corresponding leakage currents. Problem 2: The following circuit is implemented in 45 nm CMOS technology, which suffers from high leakage. For high speed, only low threshold transistors have been used. Each gate has a delay of 5ps and a leakage current of 100nA. (a) Given that a gate with high threshold transistors has a delay of 12ps and leakage of
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This note was uploaded on 09/17/2011 for the course ELEC 6970 taught by Professor Staff during the Spring '08 term at Auburn University.

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hw2prob - ELEC 5270-001/6270-001 Low-Power Design of...

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