hw2sol

# hw2sol - ELEC 5270-001/6270-001 Low-Power Design of...

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ELEC 5270-001/6270-001 Low-Power Design of Electronic Circuits Spring 2011 Homework 2 Solution Assigned 3/7/11, due 3/21/11 Problem 1: (a) In a CMOS technology all pMOS and nMOS transistors are designed to have identical “off” resistance of 10M Ω . In comparison, their “on” resistances are negligible. For a supply voltage of 1 volt, find the leakage current of a two-input NAND gate as a function of its input logic states. (b) Construct a 2-to-1 multiplexer using four two-input NAND gates. Tabulate all input vectors and their leakage currents. Identify a minimum leakage vector (MLV) and a maximum leakage vector and specify their corresponding leakage currents. Answer: (a) A CMOS NAND gate is shown below: ELEC5270-001/6270-001 Homework 2 Solution Page 1 of 9 Spring 2011 1.0 volt (VDD) 0 volt (GND) 0 1 10 M Ω 0 Ω 0 Ω 10 M Ω

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For the 01 pattern at the input as shown, the leakage resistance is 10 M Ω and the leakage current is 0.1 μ A. Leakage currents for all input patterns are shown in the following table: Input pattern Leakage current in μ A 00 0.05 01 0.1 10 0.1 11 0.2 (b) A NAND multiplexer is shown below: Following table lists all input vectors and their leakage currents: Input vector Leakage current in μ A 000 0.4 001 0.4 010 0.55 011 0.6 100 0.45 101 0.45 110 0.55 111 0.6 Average 0.5 ELEC5270-001/6270-001 Homework 2 Solution Page 2 of 9 Spring 2011 0 0.05 0 1 0.2 1 1 0.05 0.1 0 Leakage = 0.4 μ A
One of the minimum leakage vectors (MLV) is 000 and its leakage current is 0.4 μ A. It is shown in the above diagram. One of the maximum leakage vectors is 011 with a leakage of 0.6 μ A as shown below. Problem 2: The following circuit is implemented in 45 nm CMOS technology, which suffers from high leakage. For high speed, only low threshold transistors have been used. Each gate has a delay of 5ps and a leakage current of 100nA. (a) Given that a gate with high threshold transistors has a delay of 12ps and leakage of 1nA, optimally assign thresholds to gates to minimize the leakage current without increasing the critical path delay for Carry output. Assume that delay of Sum output is not critical. What is the percentage reduction in leakage power? (b) Resynthesize Carry output using two-input NAND gates directly as a function of A and B. Is it possible to further reduce leakage now? If yes, show how much reduction you can obtain.

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## hw2sol - ELEC 5270-001/6270-001 Low-Power Design of...

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