ISA for Low Power2

ISA for Low Power2 - Instruction Set Architecture (ISA) for...

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Unformatted text preview: Instruction Set Architecture (ISA) for Low Power Low Hillary Grimes III Department of Electrical and Computer Department Engineering Engineering Auburn University Outline Outline Introduction ISA Characteristics ISA Design CISC vs. RISC Register File Size Instruction Word Length Code Compression Examples: ARM, Thumb, & Thumb-2 Instruction Sets Proposed ISA Design for Low Power Proposed Future Work Future Resources ISA Characteristics ISA Three main characteristics: Register Organization # of registers & their sizes Memory Organization Address space - # of memory locations Addressablity - # of bits stored @ each location Instruction Set List of opcodes – defines instructions supported Addressing modes – defines how operand values are Addressing obtained obtained Instruction Formats – binary format for encoding instructions ISA Design ISA Typically, an ISA is designed for performance Typically, Power consumption is often ignored Power ISAs designed for performance only are ISAs generally “power hungry” generally User-Level instructions perform many operations that User-Level dominate total power dissipation dominate For low power applications, such as embedded For systems, we would like to design an ISA that lowers power dissipation without a significant reduction in performance reduction CISC vs. RISC CISC CISC Less instructions executed than in RISC (higher code Less density) density) Reduced energy consumed fetching instructions RISC More instructions than CISC, therefore more energy More consumed fetching instructions consumed Data & control paths are typically simpler, therefore Data less energy consumed per instruction less Register File Size Register Small # of general purpose registers Smaller Register File Size less energy consumed per register file access More operands fetched from memory more energy consumed by memory accesses Large # of general purpose registers Large Register File Size more energy consumed per register file access Less operands fetched from memory less energy consumed by memory accesses Instruction Word Length Instruction Required memory address space cannot be Required reduced, and usually determines register width. reduced, Many embedded processors use 32 bit Many instruction words. instruction Reducing instruction width to 16 bits requires Reducing reformatting for a 32 bit external bus to fill the memory address space requirement. memory Reduces energy consumed by each instruction fetch Reduces (by up to 50%) (by Also reduces performance by the need to reformat for Also a 32 bit external bus 32 Instruction Word Length Instruction When the energy consumed by external When memory accesses dominates the total energy consumption, energy efficiency may be significantly improved may True for small on chip caches (<8kb) Not true for larger on chip caches (16kb or Not larger). (Not as much energy saved) larger). Code Compression Code Reducing the amount of space required for Reducing porgram code reduces the amount of memory that must be fetched for program execution. that This reduces the total power consumed by This overall instruction fetches overall Two ISAs developed for the ARM processor Two family that utilize code compression: family Thumb Thumb-2 Thumb Instruction Set Thumb The Thumb instruction set is a subset of 16-bit The instructions implemented over the initial 32-bit ARM instruction set ARM Thumb code can have a higher density than Thumb most CISC processors, but the Thumb set is more limited than the 32-bit ARM Instruction set more ARM instructions can be conditionally executed, but ARM Thumb instructions are always executed Thumb The ARM set consists of 3-address instructions, but The the Thumb set contains many 2-address instructions the Thumb Instruction Set Thumb Switching between the ARM set & the Thumb Switching set is done at runtime set Mode switching between ARM & Thumb causes a Mode reduction in performance reduction When using the Thumb set, the fetched 16-bit When instruction is decoded to a 32-bit instruction & executed executed Thumb code requires only 70% of the space of Thumb ARM code ARM Thumb code uses 30% less external memory Thumb power than ARM code power Thumb-2 Instruction Set Thumb-2 Combines 16 & 32-bit instructions in a single Combines instruction set instruction 16 & 32-bit instructions can be mixed without 16 mode switching mode Thumb-2 code size is approximately equal to Thumb-2 Thumb code size Thumb Thumb-2 performance is approximately the Thumb-2 same as ARM same No performance reduction due to mode switching ARM, Thumb, & Thumb-2 Comparison Comparison Performance 100 90 80 70 60 50 ARM Thumb-2 Thumb 40 30 20 10 Vi te rb ge fB t it A lty pB Ai co m pr es s m at rix 01 Av er ag e vE n4 eg Co n jp os pf ro ta te FF Tp ul se dh ry 0 ARM, Thumb, & Thumb-2 Comparison Comparison Compiled Code Size ARM Thumb-2 Thumb Energy efficient Energy solution Thumb-2 consumes less energy than ARM from instruction fetches, while keeping the same performance as ARM performance Proposed ISA for low Power Proposed Idea behind proposed ISA: Code compression similar to, but beyond Thumb or Code Thumb-2 Thumb-2 Further reduce code space containing simple Further accumulator based functions requiring only 1 operand accumulator A more compressed code space means lower power more consumed by external memory, and hopefully lower overall power overall Proposed ISA for low Power Proposed Dual instruction sets with mode switching scheme Dual similar to Thumb similar Uncompressed Instruction Set Consists of both 16 & 32 bit instructions without the need for mode Consists switching switching Similar to Thumb-2 Compressed Instruction Set Subset of 8-bit, 1-address functions Functionality limited to simple, non-conditional accumulator based Functionality functions functions Memory accesses of 8, 16, & 32 bit widths would have to Memory be supported, along with mode switching, possibly increasing power or decreasing performance increasing Future Work Future Future work involves answering the following Future questions: questions: Can code density be significantly increased by Can reducing the code space required for simple accumulator based functions? accumulator If so, will the total power be reduced? Will processor performance be “wiped out”? What are the power requirements demanded by What supporting memory accesses of 8, 16, & 32 bit widths? widths? Would these power requirements surpass the power saved? Would this extra support have a significant impact on Would performance? performance? Future Work Future How would software design be affected How (compilers, schedulers, etc.)? (compilers, What other support would be needed? In general Would this be a realistic In energy efficient solution for a low power ISA? ISA? Resources Resources S. J. Patel, W-M. W. Hwu, and Y. N. Patt, Instruction Set S. Architectures, In General, 2002 Architectures, 2002 Bill Moyer, Low-Power Design for Embedded Processors, Low-Power Proceedings of the IEEE, vol. 89, no. 11, 2001 Flavius Gruian, Microprocessors: Low Power and Low Energy Microprocessors: Solutions, Paper for the Advanced Issues in Computer Architectures Solutions Paper course, 1999. course, T.D. Burd and R.A. Brodersen, Energy Efficient Microprocessor T.D. Design, Boston: Kluwer Academic Publishers, 2002. Design http://www.advantech.com/ePlatform/RISC/01.asp http://www.egr.msu.edu/classes/ece482/Teams/97fall/xdesign2/web/techn http://www.embedded.com/showArticle.jhtml?articleID=17701289 http://www.embedded.com/shared/printableArticle.jhtml?articleID =15200241 ...
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