Kantipudi_PTL

Kantipudi_PTL - Impact of PassTransistor Logic (PTL) on...

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Dec. 1, 2005 ELEC 6970-001 Class Presentatio 1 Impact of Pass-Transistor Logic (PTL)  on Power, Delay and Area Kalyana R Kantipudi ECE Department Auburn University
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Dec. 1, 2005 ELEC 6970-001 Class Presentatio 2 Outline: Introduction A PTL Design Need for an Improved Design A Transmission gate Design A new improved PTL Design Conclusions
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Dec. 1, 2005 ELEC 6970-001 Class Presentatio 3 Introduction: The power equation: P total  = C L V DD 2  + T sc V DD I peak  + V DD I leakage P dyn  = V DD 2 f clk . Σ α n .c n  + V DD . Σ I sc n P leakage  = V DD I subleakage   = μ 0  C ox  (W/L) V t 2  exp{(V GS -V TH )/nV t
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Dec. 1, 2005 ELEC 6970-001 Class Presentatio 4 What Can We Reduce? Activity in the circuit Switching capacitance 1. Reducing Width and Length Supply voltage reduction Short-circuit reduction
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Dec. 1, 2005 ELEC 6970-001 Class Presentatio 5 What PTL Can Offer? One pass-transistor network is enough. Reduction in number of transistors. Decrease in width and length of transistors. Results in smaller ‘input’  and ‘driving’ loads.
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Dec. 1, 2005 ELEC 6970-001 Class Presentatio 6 The Catch… Reduction in level of the signal ( V DD -V th -IR ). 1. Needs level restoration at gate outputs in order to avoid  static currents. 2. Adjust threshold voltages (V thp  > V thn ). Only one single path through each network must  be active at a time. (To avoid shorts between the  inputs) 1. A multiplexer kind of structure is to be implemented all  the time.
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Dec. 1, 2005 ELEC 6970-001 Class Presentatio 7 PTL Logic Formulation and  Implementation:
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Dec. 1, 2005 ELEC 6970-001 Class Presentatio 8
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Dec. 1, 2005
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Kantipudi_PTL - Impact of PassTransistor Logic (PTL) on...

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