lec4lp - ELEC 5970-001/6970-001(Fall 2005) Special Topics...

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9/01/05 ELEC5970-001/6970-001 Lecture 4 1 ELEC 5970-001/6970-001(Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits Low Voltage Low Power Devices Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University http://www.eng.auburn.edu/~vagrawal vagrawal@eng.auburn.edu
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9/01/05 ELEC5970-001/6970-001 Lecture 4 2 Threshold Voltage, V t + - 0 < V g < V t + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Depletion region Polysilicon gate SiO 2 p-type body + - V g > V t + + + + + + + + + + + + + - - - - - - - - - - - - - - - - - - - Depletion region + + + + + + + + + + + + + + + + + + + + + + + + + + Polysilicon gate SiO 2 p-type body V t is a function of: Dopant concentration Thickness of oxide
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9/01/05 ELEC5970-001/6970-001 Lecture 4 3 Bulk nMOSFET n+ p-type body (bulk) n+ L W SiO 2 Thickness = t ox Gate Source Drain Polysilicon V gs V gd
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9/01/05 ELEC5970-001/6970-001 Lecture 4 4 α-Power Law Model V gs > V t and V ds > V dsat = V gs –V t (Saturation region): β I ds = P c ─ ( V gs V t ) α 2 where β = μ C ox W/L For fully ON transistor, V gs = V ds = V DD : β I dsat = P c ─ (V DD – V t ) α 2 T. Sakurai and A. R. Newton, “Alpha-Power Law MOSFET Model
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lec4lp - ELEC 5970-001/6970-001(Fall 2005) Special Topics...

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