lpd_1_VHDL_LowPower

lpd_1_VHDL_LowPower - ELEC 5270-001/6270-001 Spring 09...

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Unformatted text preview: ELEC 5270-001/6270-001 Spring 09 Low-Power Design of Electronic Circuits Review of VHDL Review Nitin Yogi 01/07/2009 Spring 09, Jan 7 Spring ELEC 5270-001/6270-001 Lecture 1 (from Prof. Nelson's and Prof. ELEC Stroud's course material) Stroud's 1 HDLs in Digital System Design Model and document digital systems – Hierarchical models System, RTL (Register Transfer Level), gates – Different levels of abstraction Behavior, structure Verify circuit/system design via simulation Synthesize circuits from HDL models Synthesize Spring 09, Jan 7 Spring ELEC 5270-001/6270-001 Lecture 1 (from Prof. Nelson's and Prof. ELEC Stroud's course material) Stroud's 2 Hardware Description Languages VHDL = VHSIC Hardware Description Language VHDL (VHSIC = Very High Speed Integrated Circuits) (VHSIC – – – Developed by DOD from 1983 – based on ADA IEEE Standard 1076-1987/1993/200x Based on the ADA language Verilog – created in 1984 by Philip Moorby of Verilog Gateway Design Automation (merged with Cadence) Cadence) – IEEE Standard 1364-1995/2001/2005 – Based on the C language – IEEE P1800 “System Verilog” in voting stage & will be IEEE merged with 1364 merged Spring 09, Jan 7 Spring ELEC 5270-001/6270-001 Lecture 1 (from Prof. Nelson's and Prof. ELEC Stroud's course material) Stroud's 3 Other VHDL Standards 1076.1–1999: VHDL-AMS (Analog & MixedSignal Extensions) 1076.2–1996: Std. VHDL Mathematics –1996: Packages Packages 1076.3-1997: Std. VHDL Synthesis Packages 1076.4-1995: Std. VITAL Modeling Specification -1995: (VHDL Initiative Towards ASIC Libraries) (VHDL 1076.6-1999: Std. for VHDL Register Transfer -1999: Level (RTL) Synthesis Level 1164-1993: Std. Multivalue Logic System for -1993: VHDL Model Interoperability VHDL Spring 09, Jan 7 Spring ELEC 5270-001/6270-001 Lecture 1 (from Prof. Nelson's and Prof. ELEC Stroud's course material) Stroud's 4 Anatomy of a VHDL Model “Entity” describes the external view of a Entity” external design/component design/component “Architecture” describes the internal Architecture” internal behavior/structure of the component behavior/structure Example: Example: 1-bit full adder 1-bit Full Adder A Sum B Cin Spring 09, Jan 7 Spring Cout ELEC 5270-001/6270-001 Lecture 1 (from Prof. Nelson's and Prof. ELEC Stroud's course material) Stroud's 5 Entity Inputs/Outputs External view comprises input/output signals External (“ports”) (“ports”) A “port” is defined by its signal name, direction “port” and type: port_name: direction data_type; port_name: – direction: in - driven into the entity from an external source out - driven from within the entity out inout - bidirectional – drivers within the entity and external – data_type: any scalar or aggregate signal type Spring 09, Jan 7 Spring ELEC 5270-001/6270-001 Lecture 1 (from Prof. Nelson's and Prof. ELEC Stroud's course material) Stroud's 6 Built-in Data Types Scalar (single-value) signal types: – bit - values are ‘0’ or ‘1’ – boolean – values are TRUE and FALSE – integer Aggregate (multi-value) signal types: – bit_vector – array of bits signal b: bit_vector(7 downto 0); signal c: bit_vector(0 to 7); Spring 09, Jan 7 Spring ELEC 5270-001/6270-001 Lecture 1 (from Prof. Nelson's and Prof. ELEC Stroud's course material) Stroud's 7 IEEE Standard 1164 Data Types Type std_logic data values: Type std_logic ‘U’, ‘X’ – uninitialized/unknown ‘0’, ‘1’ – strongly-driven 0/1 ‘L’, ‘H’ – weakly-driven 0/1 (resistive) ‘Z’, ‘W’ - strong/weak “floating” ‘-’ - don’t care Type std_logic_vector is array of std_logic Include package: library IEEE; use IEEE.std_logic_1164.all; Spring 09, Jan 7 Spring ELEC 5270-001/6270-001 Lecture 1 (from Prof. Nelson's and Prof. ELEC Stroud's course material) Stroud's 8 User-Defined Data Types Any abstract data type can be created Examples: type mnemonic is (add,sub,mov,jmp); signal op: mnemonic; type byte is array(0 to 7) of bit; signal dbus: byte; Spring 09, Jan 7 Spring ELEC 5270-001/6270-001 Lecture 1 (from Prof. Nelson's and Prof. ELEC Stroud's course material) Stroud's 9 “entity” Format entity entity_name is generic (generic_name: type :=default_value; … generic_name: mode signal_type); port (signal_name: mode signal_type; … signal_name: mode signal_type); end entity entity_name; Spring 09, Jan 7 Spring ELEC 5270-001/6270-001 Lecture 1 (from Prof. Nelson's and Prof. ELEC Stroud's course material) Stroud's 10 “entity” Example (1-Bit Full Adder) Full Adder A Sum B entity full_add1 is port ( ­­ I/O ports a: in bit; ­­ a input b: in bit; ­­ b input cin: in bit; ­­ carry input sum: out bit; ­­ sum output cout: out bit); ­­ carry output end full_add1 ; Spring 09, Jan 7 Spring Cin ELEC 5270-001/6270-001 Lecture 1 (from Prof. Nelson's and Prof. ELEC Stroud's course material) Stroud's Cout 11 “architecture” Format architecture architecture_name of entity_name is -- data type definitions (ie, states, arrays, etc.) -- internal signal declarations -- component declarations -- function and procedure declarations begin -- behavior of the model is described here using: -- component instantiations -- concurrent statements -- processes end architecture architecture_name; Spring 09, Jan 7 Spring ELEC 5270-001/6270-001 Lecture 1 (from Prof. Nelson's and Prof. ELEC Stroud's course material) Stroud's 12 “architecture” Example (Behavioral) architecture dataflow of full_add1 is begin sum <= a xor b xor cin after 1 ns; cout <= (a and b) or (a and cin) or (b and cin) after 1 ns; (b end; Spring 09, Jan 7 Spring ELEC 5270-001/6270-001 Lecture 1 (from Prof. Nelson's and Prof. ELEC Stroud's course material) Stroud's 13 Example Using an Internal Signal architecture dataflow of full_add1 is signal x1: bit; -- internal signal signal begin x1 <= a xor b after 1 ns; sum <= x1 xor cin after 1 ns; sum x1 cout <= (a and b) or (a and cin) or (b and cin) after 1 ns; (b end; Spring 09, Jan 7 Spring ELEC 5270-001/6270-001 Lecture 1 (from Prof. Nelson's and Prof. ELEC Stroud's course material) Stroud's 14 Event-Driven Simulation Example a <= b after 1ns; c <= a after 1ns; Time a T ‘0’ ‘0’ T+1 ‘0’ T+1 T+2 ‘1’ T+3 ‘1’ T+3 b ‘0’ ‘1’ ‘1’ ‘1’ c ‘0’ ‘0’ ‘0’ ‘1’ Spring 09, Jan 7 Spring ELEC 5270-001/6270-001 Lecture 1 (from Prof. Nelson's and Prof. ELEC Stroud's course material) Stroud's - external event on b - resulting event on a - resulting event on c 15 “architecture” Example (Structural) architecture structure of full_add1 is component xor -- declare component to be used port (x,y: in bit; z: out bit); end component; signal x1: bit;-- signal internal to this component begin G1: xor port map (A, B, X1); -- instantiate 1st xor gate G2: xor port map (X1, Cin, Sum); -- instantiate 2nd xor gate …add circuit for carry output… end; A X1 Cin Spring 09, Jan 7 Spring ELEC 5270-001/6270-001 Lecture 1 (from Prof. Nelson's and Prof. ELEC Stroud's course material) Stroud's Sum 16 Example: D Flip-Flop entity DFF is port (Preset: in bit; Clear: in bit; Clear: Clock: in bit; Clock: Data: in bit; Data: Q: out bit; Q: Qbar: out bit); Qbar: end DFF; Spring 09, Jan 7 Spring Preset Data Q Clock Qbar Clear ELEC 5270-001/6270-001 Lecture 1 (from Prof. Nelson's and Prof. ELEC Stroud's course material) Stroud's 17 7474 D Flip-Flop Equations architecture eqns of DFF is signal A,B,C,D: bit; signal QInt, QBarInt: bit; begin A <= not (Preset and D and B) after 1 ns; B <= not (A and Clear and Clock) after 1 ns; C <= not (B and Clock and D) after 1 ns; D <= not (C and Clear and Data) after 1 ns; Qint <= not (Preset and B and QbarInt) after 1 ns; QBarInt <= not (QInt and Clear and C) after 1 ns; Q <= QInt; QBar <= QBarInt; end; ELEC 5270-001/6270-001 Lecture 1 (from Prof. Nelson's and Prof. ELEC Spring 09, Jan 7 Spring Stroud's course material) Stroud's 18 4-bit Register (Structural Model) 4-bit entity Register4 is entity port ( D: in bit_vector(0 to 3); port Q: out bit_vector(0 to 3); Q: Clk: in bit; Clk: Clr: in bit; Clr: Pre: in bit); Pre: D(3) D(2) end Register4; D(1) D(0) CLK PRE CLR Q(3) Spring 09, Jan 7 Spring Q(2) Q(1) ELEC 5270-001/6270-001 Lecture 1 (from Prof. Nelson's and Prof. ELEC Stroud's course material) Stroud's Q(0) 19 Register Architecture architecture structure of Register4 is component DFF -- declare library component to be used port (Preset: in bit; Clear: in bit; Clear: Clock: in bit; Clock: Data: in bit; Data: Q: out bit; Q: Qbar: out bit); Qbar: end component; end signal Qbar: bit_vector(0 to 3); -- dummy for unused FF output -begin -- Signals connected to ports in order listed above begin -F3: DFF port map (Pre, Clr, Clk, D(3), Q(3), Qbar(3)); F2: DFF port map (Pre, Clr, Clk, D(2), Q(2), Qbar(2)); F1: DFF port map (Pre, Clr, Clk, D(1), Q(1), Qbar(1)); F0: DFF port map (Pre, Clr, Clk, D(0), Q(0), Qbar(0)); end; Spring 09, Jan 7 Spring ELEC 5270-001/6270-001 Lecture 1 (from Prof. Nelson's and Prof. ELEC Stroud's course material) Stroud's 20 Register Architecture (short cut – “generate” statement) begin for k in 0 to 3 generate F: DFF port map (Pre, Clr, Clk, D(k), Q(k), Qbar(k)); F: end generate; end; Generates multiple copies of the given statement(s) Value of k inserted where specified Iteration number k is appended to each label F Result is identical to previous example Spring 09, Jan 7 Spring ELEC 5270-001/6270-001 Lecture 1 (from Prof. Nelson's and Prof. ELEC Stroud's course material) Stroud's 21 Statements Used for Modeling Concurrent statements – Concurrent assignments – with – select – when – when – else Sequential statements using “process” – – – – if – then – else case – when for – loop while - loop Spring 09, Jan 7 Spring ELEC 5270-001/6270-001 Lecture 1 (from Prof. Nelson's and Prof. ELEC Stroud's course material) Stroud's 22 Concurrent Assignments A <= not (Preset and D and B) after 1 ns; B <= not (A and Clear and Clock) after 1 ns; C <= not (B and Clock and D) after 1 ns; D <= not (C and Clear and Data) after 1 ns; Spring 09, Jan 7 Spring ELEC 5270-001/6270-001 Lecture 1 (from Prof. Nelson's and Prof. ELEC Stroud's course material) Stroud's 23 With – select - when with S select y <= a after 1 ns when “00”, b after 1 ns when “01”, c after 1 ns when “10”, d after 1 ns when “11”; (or: d after 1 ns when others;) (or: 4-to-1 Mux a 00 b 01 c 10 d 11 y S Spring 09, Jan 7 Spring ELEC 5270-001/6270-001 Lecture 1 (from Prof. Nelson's and Prof. ELEC Stroud's course material) Stroud's 24 When - else y <= a after 1 ns when (S=“00”) else b after 1 ns when (S=“01”) else c after 1 ns when (S=“10”) else d after 1 ns; 4-to-1 Mux 00 b 01 c Any boolean expression can be used for each condition. a 10 d 11 y S Ex. y <= a after 1 ns when (F=‘1’) and (G=‘0’) … Ex. <= Spring 09, Jan 7 Spring ELEC 5270-001/6270-001 Lecture 1 (from Prof. Nelson's and Prof. ELEC Stroud's course material) Stroud's 25 Tristate Buffer Example library ieee; use ieee.std_logic_1164.all; entity tristate is port ( a: in bit; port y: out std_logic; y: en: in bit); en: end tristate; a y en architecture a1 of tristate is begin y <= a after 1 ns when (en=‘1’) else ‘Z’ after 1 ns; end; -- Error: Type mismatch between y and a Spring 09, Jan 7 Spring ELEC 5270-001/6270-001 Lecture 1 (from Prof. Nelson's and Prof. ELEC Stroud's course material) Stroud's 26 Tristate Buffer Example (Correct) Tristate (Correct) library ieee; use ieee.std_logic_1164.all; entity tristate is port ( a: in bit; port y: out std_logic; y: en: in bit); en: end tristate; a y en architecture a1 of tristate is begin y <= ‘0’ after 1 ns when (en=‘1’) and (a=‘0’) else ‘1’ after 1 ns when (en=‘1’) and (a=‘1’) else ‘Z’ after 1 ns; end; Spring 09, Jan 7 Spring ELEC 5270-001/6270-001 Lecture 1 (from Prof. Nelson's and Prof. ELEC Stroud's course material) Stroud's 27 Tristate Bus Buffer Example library ieee; use ieee.std_logic_1164.all; entity tristate is port ( a: in bit_vector(0 to 7); port y: out std_logicvector(0 to 7); y: en: in bit); en: end tristate; a y en architecture a1 of tristate is begin y <= to_stdlogicvector(a) after 1 ns when (en=‘1’) else <= to_stdlogicvector(a) “ZZZZZZZZ” after 1 ns; end; Spring 09, Jan 7 Spring ELEC 5270-001/6270-001 Lecture 1 (from Prof. Nelson's and Prof. ELEC Stroud's course material) Stroud's 28 VHDL “Process” Construct Allows conventional programming language Allows methods to describe circuit behavior methods Supported language constructs (“sequential Supported statements”) – only allowed within a process: only – – – – – variable assignment if-then-else (elsif) case statement while (condition) loop for (range) loop Spring 09, Jan 7 Spring ELEC 5270-001/6270-001 Lecture 1 (from Prof. Nelson's and Prof. ELEC Stroud's course material) Stroud's 29 Process Format [label:] process (sensitivity list) declarations begin begin sequential statements end process; end Process statements executed once at start of Process simulation simulation Process halts at “end” until an event occurs on a Process signal in the “sensitivity list” signal Spring 09, Jan 7 Spring ELEC 5270-001/6270-001 Lecture 1 (from Prof. Nelson's and Prof. ELEC Stroud's course material) Stroud's 30 Using a “process” to Model Using Sequential Behavior Sequential entity DFF is entity port (D,CLK: in std_logic; port Q: out std_logic); Q: end DFF; D Q CLK architecture behave of DFF is begin process(clk) -- “process sensitivity list” begin iif (clk’event and clk=‘1’) then f (clk’event Q <= D after 1 ns; <= end if; end process; end; Process statements executed sequentially (sequential statements) clk’event is an attribute of signal clk which is TRUE if an event has occurred on clk at the current clk’event simulation time simulation Spring 09, Jan 7 Spring ELEC 5270-001/6270-001 Lecture 1 (from Prof. Nelson's and Prof. ELEC Stroud's course material) Stroud's 31 Alternative to Sensitivity List entity DFF is entity port (D,CLK: in std_logic; port Q: out std_logic); Q: D end DFF; architecture behave of DFF is CLK begin process -- no “sensitivity list” begin wait on clk; -- suspend process until event on clk if (clk=‘1’) then Q <= D after 1 ns; <= end if; end process; end; Q Other “wait” formats: wait until (clk’event and clk=‘1’) wait for 20 ns; Process executes endlessly if no sensitivity list or wait statement! Spring 09, Jan 7 Spring ELEC 5270-001/6270-001 Lecture 1 (from Prof. Nelson's and Prof. ELEC Stroud's course material) Stroud's 32 D Latch vs. D Flip-Flop entity Dlatch is entity port (D,CLK: in std_logic; port Q: out std_logic); Q: end Dlatch; architecture behave of Dlatch is begin process(D, clk) begin iif (clk=‘1’) then f (clk=‘1’) Q <= D after 1 ns; <= end if; end process; end; D Q CLK For latch, Q changes whenever the latch is enabled by CLK=‘1’ (rather than being edge-triggered) Spring 09, Jan 7 Spring ELEC 5270-001/6270-001 Lecture 1 (from Prof. Nelson's and Prof. ELEC Stroud's course material) Stroud's 33 Synchronous vs. Asynchronous Synchronous Flip-Flop Inputs Flip-Flop entity DFF is entity port (D,CLK: in std_logic; port CLR PRE,CLR: in std_logic; PRE,CLR: D Q Q: out std_logic); Q: end DFF; CLK architecture behave of DFF is PRE begin process(clk,PRE,CLR) begin iif (CLR=‘0’) then -- CLR has precedence f -Q <= ‘0’ after 1 ns; <= elsif (PRE=‘0’) then -- Then PRE has precedence elsif -Q <= ‘1’ after 1 ns; <= elsif (clk’event and clk=‘1’) then Q <= D after 1 ns; -- Only if CLR=PRE=‘1’ -end if; end process; end; ELEC 5270-001/6270-001 Lecture 1 (from Prof. Nelson's and Prof. ELEC Spring 09, Jan 7 Spring Stroud's course material) Stroud's 34 Configurable N-bit Register entity REG is entity generic (N:integer := 4) generic port (D: in std_logic_vector(N-1 downto 0); port CLK: in std_logic; CLK: Q: out std_logic_vector(N-1 downto 0)); Q: end REG; architecture behave of REG is begin process(clk) begin if (clk’event and clk=‘1’) then Q <= D after 1 ns; end if; end end process; end; Spring 09, Jan 7 Spring ELEC 5270-001/6270-001 Lecture 1 (from Prof. Nelson's and Prof. ELEC Stroud's course material) Stroud's 35 Signals vs Variables Signals – – – Signals follow the notion of ‘event scheduling’ An event is characterized by a (time,value) pair Signal assignment example: X <= Xtmp after <time>; means means Schedule the assignment of the value of signal Schedule Xtmp to signal X at (Current time + <time>) Xtmp Variables – – Variables do not have notion of ‘events’ Variables can be defined and used only inside the Variables process block and some other special blocks. process Spring 09, Jan 7 Spring ELEC 5270-001/6270-001 Lecture 1 (from Prof. Nelson's and Prof. ELEC Stroud's course material) Stroud's 36 Using a “variable” to Describe Using Sequential Behavior Within a Process Sequential cnt: process(clk) variable count_v: std_logic_vector; -- internal counter variable variable -signal count_s: std_logic_vector; -- internal counter signal signal -begin begin if clk=‘1’ and clk’event then if load=‘1’ then count_v := Din; count_v count_s <= Din after 1ns; count_s elsif cnt=‘1’ then count_v := count_v + 1; -- use appropriate package for ‘+’ count_v -count_s <= count_s + 1 after 1ns; count_s end if; end if; end DoutA <= count_v after 1ns; Time clk load Din count_v count_s DoutA DoutB DoutA DoutB <= count_s after 1ns; 0DoutB 0 1 1 0 0 0 0 end process; end 0 1 1 1 0 0 0 1 Spring 09, Jan 7 Spring 1 1 1 1 1 1 1 0 ELEC 5270-001/6270-001 Lecture 1 (from Prof. Nelson's and Prof. ELEC Stroud's course material) Stroud's 37 Sequential Statements in Process iif-then-elsif-else statement f-then-elsif-else statement iif condition then f condition (... sequence of statements...) (... elsif condition then condition (... sequence of statements...) (... else else (... sequence of statements...) (... end if; case statement statement case expression is case expression when choices => sequence of statements choices sequence when choices => sequence of statements choices sequence ... when others => sequence of statements others sequence end case; end Spring 09, Jan 7 Spring ELEC 5270-001/6270-001 Lecture 1 (from Prof. Nelson's and Prof. ELEC Stroud's course material) Stroud's 38 Sequential Statements in Process while loop while loop [label:] while condition loop condition ... sequence of statements ... end loop [label]; end for loop loop [label:] for loop_variable in range loop for ... sequence of statements... end loop [label]; Spring 09, Jan 7 Spring ELEC 5270-001/6270-001 Lecture 1 (from Prof. Nelson's and Prof. ELEC Stroud's course material) Stroud's 39 Modeling Finite State Machines Modeling (Synchronous Sequential Circuits) (Synchronous Inputs x Outputs z Comb. Logic Present State y Next State Y FFs Clock Next State Y = f(x,y) Spring 09, Jan 7 Spring ELEC 5270-001/6270-001 Lecture 1 (from Prof. Nelson's and Prof. ELEC Stroud's course material) Stroud's 40 Synchronous Sequential Circuit Synchronous (FSM) Example (FSM) 0 /0 X /Z A 1 /1 1 /0 0 /0 0 /0 B C P re se n t s ta te A B C 0 In p u t x A /0 A /0 C /0 1 B /0 C /1 A /1 N e x t s ta te /o u tp u t 1 /1 Spring 09, Jan 7 Spring ELEC 5270-001/6270-001 Lecture 1 (from Prof. Nelson's and Prof. ELEC Stroud's course material) Stroud's 41 FSM Example – “entity” Definition entity seqckt is port ( port x: in bit; z: out bit; clk: in bit ); end seqckt; Spring 09, Jan 7 Spring -- FSM input -- FSM output -- clock ELEC 5270-001/6270-001 Lecture 1 (from Prof. Nelson's and Prof. ELEC Stroud's course material) Stroud's 42 FSM Example - Behavioral Model architecture behave of seqckt is type states is (A,B,C); -- symbolic state names signal curr_state,next_state: states; begin -- Model the memory elements of the FSM process (clk) begin if (clk’event and clk=‘1’) then pres_state <= next_state; end if; end process; (continue on next slide) Spring 09, Jan 7 Spring ELEC 5270-001/6270-001 Lecture 1 (from Prof. Nelson's and Prof. ELEC Stroud's course material) Stroud's 43 FSM Example - Continued -- Model the next-state and output functions of the FSM process (x, pres_state) -- function inputs process -begin case pres_state is -- describe each state case when A => if (x = ‘0’) then when z <= ‘0’; <= next_state <= A; else -- (x = ‘1’) -z <= ‘0’; next_state <= B; end if; end (continue next slide for pres_state = B and C) Spring 09, Jan 7 Spring ELEC 5270-001/6270-001 Lecture 1 (from Prof. Nelson's and Prof. ELEC Stroud's course material) Stroud's 44 FSM Example (Continued) when B => if (x=‘0’) then when z <= ‘0’; next_state <= A; else else z <= ‘1’; next_state <= C; end if; end when C => if (x=‘0’) then z <= ‘0’; next_state <= C; else else z <= ‘1’; next_state <= A; end if; end end case; end end process; end end; Spring 09, Jan 7 Spring ELEC 5270-001/6270-001 Lecture 1 (from Prof. Nelson's and Prof. ELEC Stroud's course material) Stroud's 45 64K x 8 Memory Example library ieee; use ieee.std_logic_1164.all; use work.qsim_logic.all; -- package with to_integer() func entity memory8 is port (dbus: inout std_logic_vector(0 to 7); port abus: in std_logic_vector(0 to 15); abus: ce: in bit; -- active low chip enable ce: oe: in bit; -- active low output enable oe: we: in bit); -- active low write enable we: end memory8; Spring 09, Jan 7 Spring ELEC 5270-001/6270-001 Lecture 1 (from Prof. Nelson's and Prof. ELEC Stroud's course material) Stroud's 46 64K x 8 Memory Example architecture reglevel of memory8 is begin process (ce,oe,we,abus,dbus) process type mem is array(natural range <>) of std_logic_vector(0 to 7); type variable M: mem(0 to 65535); variable begin begin if (ce='0') and (oe='0') then -- read enabled -dbus <= M(to_integer(abus)); -- drive the bus dbus elsif (ce='0') and (we='0') then -- write enabled -dbus <= "ZZZZZZZZ"; -- disable drivers dbus M(to_integer(abus)) := dbus; -- write to M M(to_integer(abus)) else else dbus <= "ZZZZZZZZ"; --disable drivers dbus end if; end end process; end end; Spring 09, Jan 7 Spring ELEC 5270-001/6270-001 Lecture 1 (from Prof. Nelson's and Prof. ELEC Stroud's course material) Stroud's 47 Miscellaneous VHDL Items Subtypes of previously-defined data types subtype int3 is integer range 0 to 7; Use of “alias” for existing elements signal instruc: bit_vector(0 to 31); alias opcode: bit_vector(0 to 5) is instruc(0 to 5); alias rd: bit_vector(0 to 4) is instruc(6 to 10); alias rs: bit_vector(0 to 4) is instruc(11 to 15); Fill a bit_vector with a constant (right-most bits): A <= (‘0’,’1’,’1’, others => ‘0’); B(15 downto 0) <= C(15 downto 0); B(31 downto 16) <= (others => C(15)); -- sign extension! Concatenate bits and bit_vectors A <= B & C(0 to 3) & “00”; -- A is 16 bits, B is 10 bits Spring 09, Jan 7 Spring ELEC 5270-001/6270-001 Lecture 1 (from Prof. Nelson's and Prof. ELEC Stroud's course material) Stroud's 48 Unconstrained Bit Vectors Allows a generic component with different sizes: entity mux is port (a,b: in bit_vector; -- unconstrained c: out bit_vector; s: in bit ); end mux; end architecture x of mux is begin c <= a when (s=‘0’) else b; end; Spring 09, Jan 7 Spring ELEC 5270-001/6270-001 Lecture 1 (from Prof. Nelson's and Prof. ELEC Stroud's course material) Stroud's 49 Unconstrained Bit Vectors Vector constrained when instantiated: architecture struct of my_design is signal s1,s2: bit; signal signal a5,b5,c5: bit_vector (0 to 4); signal a32,b32,c32: bit_vector (0 to 31); component mux component port (a,b: in bit_vector; -- unconstrained port c: out bit_vector; s: in bit ); end component; end begin M5: mux port map (a5,b5,c5,s1); -- 5-bit mux M32: mux port map (a32,b32,c32,s2); -- 32-bit mux end; Spring 09, Jan 7 Spring ELEC 5270-001/6270-001 Lecture 1 (from Prof. Nelson's and Prof. ELEC Stroud's course material) Stroud's 50 Other VHDL Resources VHDL mini-reference on Prof. Nelson’s website website – http://www.eng.auburn.edu/department/ee/mgc/vhdl.html VHDL resources on Prof. Stroud’s website VHDL Prof. – http://www.eng.auburn.edu/~strouce/elec4200.html VHDL Tutorial: Learn by Example VHDL by Weijun Zhang by – http://esd.cs.ucr.edu/labs/tutorial/ Spring 09, Jan 7 Spring ELEC 5270-001/6270-001 Lecture 1 (from Prof. Nelson's and Prof. ELEC Stroud's course material) Stroud's 51 ...
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This note was uploaded on 09/17/2011 for the course ELEC 6970 taught by Professor Staff during the Spring '08 term at Auburn University.

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