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Unformatted text preview: ELEC 5270/6270 Spring 2011
LowPower Design of Electronic Circuits GateLevel Power Analysis
GateLevel
Vishwani D. Agrawal James J. Danaher Professor
Dept. of Electrical and Computer Engineering
Auburn University, Auburn, AL 36849
vagrawal@eng.auburn.edu
http://www.eng.auburn.edu/~vagrawal/COURSE/E6270_Spr11/course.html
Copyright Agrawal, 2007
Copyright ELEC5270001/6270001 Jan 24 Lecture 3 1 Power Analysis Motivation: Specification Optimization Reliability Applications Design analysis and optimization Physical design Packaging Test
Copyright Agrawal, 2007
Copyright ELEC5270001/6270001 Jan 24 Lecture 3 2 Abstraction, Complexity, Accuracy
Abstraction level
Algorithm Computing resources Analysis accuracy Least Worst Most Best Software and system
Hardware behavior
Register transfer
Logic
Circuit
Device
Copyright Agrawal, 2007
Copyright ELEC5270001/6270001 Jan 24 Lecture 3 3 Circuit/device Spice level analysis Circuit
Circuit modeled as network of transistors, capacitors, resistors
and voltage/current sources.
and Node current equations using Kirchhoff’s current law. Average and instantaneous power computed from supply voltage
Average
and device current.
and Analysis Used Original is accurate but expensive
to characterize parts of a larger circuit. references: L.
L. W. Nagel and D. O. Pederson, “SPICE – Simulation Program
With Integrated Circuit Emphasis,” Memo ERLM382, EECS
Dept., University of California, Berkeley, Apr. 1973.
Dept., L. W. Nagel, SPICE 2, A Computer program to Simulate
L.
Semiconductor Circuits, PhD Dissertation, University of
Semiconductor
PhD
California, Berkeley, May 1975.
California,
Copyright Agrawal, 2007
Copyright ELEC5270001/6270001 Jan 24 Lecture 3 4 Logic Model of MOS Circuit
Logic
pMOS FETs VDD
a a
Ca
b Cb nMOS
FETs c
Cc
Cd Ca , Cb , Cc and Cd are
node capacitances
Copyright Agrawal, 2007
Copyright b Da
Db c Dc Da and Db are
interconnect or
propagation delays
Dc is inertial delay
of gate ELEC5270001/6270001 Jan 24 Lecture 3 5 Spice Characterization of a 2Input
Spice
NAND Gate
NAND
Input data pattern Delay (ps) Dynamic energy (pJ) a=b=0→1 69 1.55 a = 1, b = 0 → 1 62 1.67 a = 0 → 1, b = 1
1, 50 1.72 a=b=1→0 35 1.82 a = 1, b = 1 → 0 76 1.39 a = 1 → 0, b = 1 57 1.94 Copyright Agrawal, 2007
Copyright ELEC5270001/6270001 Jan 24 Lecture 3 6 Spice Characterization (Cont.)
Input data pattern Static power (pW) a=b=0 5.05 a = 0, b = 1
0, 13.1 a = 1, b = 0 5.10 a=b=1 28.5 Copyright Agrawal, 2007
Copyright ELEC5270001/6270001 Jan 24 Lecture 3 7 SwitchLevel Partitioning Circuit partitioned into channelconnected components
Circuit
for Spice characterization.
for
Reference: R. E. Bryant, “A SwitchLevel Model and
Reference:
Simulator for MOS Digital Systems,” IEEE Trans.
Computers, vol. C33, no. 2, pp. 160177, Feb. 1984.
Computers Internal
switching
nodes not
seen by
logic
simulator Copyright Agrawal, 2007
Copyright G2 G1 G3 ELEC5270001/6270001 Jan 24 Lecture 3 8 Delay and DiscreteEvent Simulation
Inputs (NAND gate)
Transient
region a
b
c (CMOS) Logic simulation c (zero delay)
c (unit delay)
X c (multiple delay) Unknown (X) c (minmax delay)
0 Copyright Agrawal, 2007
Copyright 5 ELEC5270001/6270001 Jan 24 Lecture 3 rise=5, fall=5
min =2, max =5
Time units
9 EventDriven Simulation Example
Scheduled
events
2 e =1
g =1 2 2 d=0
4 b =1 f =0 Time stack a =1
c =1→0 t=0
1
2
3
4
5
6
7
8 Activity
list c=0 d, e d = 1, e = 0 f, g g=0
f=1 g g=1 g
0
Copyright Agrawal, 2007
Copyright 4 8 Time, t ELEC5270001/6270001 Jan 24 Lecture 3 10 Time Wheel (Circular Stack)
Current
time
pointer max
t=0
1 Event linklist 2
3
4
5
6
7 Copyright Agrawal, 2007
Copyright ELEC5270001/6270001 Jan 24 Lecture 3 11 GateLevel Power Analysis Presimulation analysis: Partition
Partition circuit into channel connected
components.
components. Determine node capacitances from layout
Determine
analysis (accurate) or from wireload model*
(approximate).
(approximate). Determine dynamic and static power from Spice
Determine
for each gate.
for Determine gate delays using Spice or Elmore
Determine
delay model.
delay
* Wireload model estimates capacitance of a net by its pincount. See Yeap, p. 39.
Copyright Agrawal, 2007
Copyright ELEC5270001/6270001 Jan 24 Lecture 3 12 Elmore Delay Model W. Elmore, “The Transient Response of Damped Linear Networks
W.
with Particular Regard to Wideband Amplifiers,” J. Appl. Phys., vol.
J.
.,
19, no.1, pp. 5563, Jan. 1948.
19,
2
R2
C2
1
R1
s
4
R4
C1
Shared resistance: C4 R3
3
C3 R45 = R1 + R3
R15 = R1
R34 = R1 + R3
Copyright Agrawal, 2007
Copyright R5
5
C5 ELEC5270001/6270001 Jan 24 Lecture 3 13 Elmore Delay Formula
N
Delay at node k = 0.69 Σ Cj × Rjk
j =1
where N = number of capacitive nodes in the network
Example:
Delay at node 5 = 0.69[R1 C1 + R1 C2 + (R1+R3)C3 + (R1+R3)C4
+ (R1+R3+R5)C5] Copyright Agrawal, 2007
Copyright ELEC5270001/6270001 Jan 24 Lecture 3 14 GateLevel Power Analysis (Cont.) Run
Run discreteevent (eventdriven) logic
simulation with a set of input vectors.
simulation Monitor the toggle count of each net and obtain
Monitor
capacitive component of power dissipation:
capacitive
Pcap = Σ Ck V 2 f
all nodes k Where: Ck is the total node capacitance being switched, as
determined by the simulator.
determined V is the supply voltage. f is the clock frequency, i.e., the number of vectors applied
per unit time
per
Copyright Agrawal, 2007
Copyright ELEC5270001/6270001 Jan 24 Lecture 3 15 GateLevel Power Analysis (Cont.) Monitor
Monitor dynamic energy events at the
input of each gate and obtain internal
switching (short circuit) power dissipation:
switching
Pint = Σ
Σ
E(g,e) F(g,e)
E(g,e)
gates g events e Where
E(g,e)
E(g,e) = energy of event e of gate g, precomputed
precomputed
shortcircuit power from Spice.
shortcircuit
F(g,e) = occurrence frequency of the event e at
F(g,e) occurrence
gate g, observed by logic simulation.
gate observed
Copyright Agrawal, 2007
Copyright ELEC5270001/6270001 Jan 24 Lecture 3 16 GateLevel Power Analysis (Cont.) Monitor
Monitor the static power dissipation state of each
gate and obtain the static power dissipation:
gate
Pstat = Σ
gates g Σ P(g,s) T(g,s)/ T
P(g,s)
states s Where P(g,s)
P(g,s) = static power dissipation of gate g for state s,
static
for
obtained from Spice.
obtained T(g,s) = duration of state s at gate g, obtained from logic
T(g,s) duration
at
simulation.
simulation T = number of vectors × vector period.
Copyright Agrawal, 2007
Copyright ELEC5270001/6270001 Jan 24 Lecture 3 17 GateLevel Power Analysis Sum up all three components of power:
P = Pcap + Pint + Pstat
cap References: A.
A. Deng, “Power Analysis for CMOS/BiCMOS Circuits,” Proc.
International Workshop Low Power Design, 1994.
International J. Benkoski, A. C. Deng, C. X. Huang, S. Napper and J.
J.
Tuan, “Simulation Algorithms, Power Estimation and
Diagnostics in PowerMill,” Proc. PATMOS, 1995.
Proc. C. X. Huang, B. Zhang, A. C. Deng and B. Swirski, “The
C.
Design and Implementation of PowerMill,” Proc. International
Symp. Low Power Design, 1995, pp. 105109.
Symp.
Copyright Agrawal, 2007
Copyright ELEC5270001/6270001 Jan 24 Lecture 3 18 Probabilistic Analysis View signals as a random processes Prob{s(t) = 1} = p1
p0 = 1 – p1 C 0→1 transition probability = (1 – p1) p1
Power, P = (1 – p1) p1 CV f Copyright Agrawal, 2007
Copyright ELEC5270001/6270001 Jan 24 Lecture 3 19 Source of Inaccuracy
p1 = 0.5 P = 0.5CV 2 fck
1/fck p1 = 0.5 P = 0.33CV 2 fck p1 = 0.5 P = 0.167CV 2 fck Observe that the formula, Power, P = (1 – p1) p1 C V f = 0.25 C V f Copyright Agrawal, 2007
Copyright ELEC5270001/6270001 Jan 24 Lecture 3 20 Switching Frequency
Number of transitions per unit time:
T = N(t)
──
t For a continuous signal:
T = lim
t→∞ N(t)
───
t T is defined as transition density. Copyright Agrawal, 2007
Copyright ELEC5270001/6270001 Jan 24 Lecture 3 21 Static Signal Probabilities Observe
Observe signal for interval t 0 + t 1 Signal
Signal is 1 for duration t 1 Signal is 0 for duration t 0
Signal Signal probabilities:
p 1 = t 1/(t 0 + t 1)
1/(
1) p 0 = t 0/(t 0 + t 1) = 1 – p 1
0/( Copyright Agrawal, 2007
Copyright ELEC5270001/6270001 Jan 24 Lecture 3 22 Static Transition Probabilities Transition probabilities: T 01 = p 0 Prob{signal is 1  signal was 0} = p 0 p1 T 10 = p 1 Prob{signal is 0  signal was 1} = p 1 p 0 T = T 01 + T 10 = 2 p 0 p 1 = 2 p 1 (1 – p 1)
1) Copyright Agrawal, 2007
Copyright ELEC5270001/6270001 Jan 24 Lecture 3 23 Static Transition Probability
f = p 1 (1 – p 1 ) 0.25
0.2
0.1
0.0
0 Copyright Agrawal, 2007
Copyright 0.25 0.5
p1 0.75 ELEC5270001/6270001 Jan 24 Lecture 3 1.0 24 Inaccuracy in Transition Probability
p1 = 0.5 T = 1.0
1/fck p1 = 0.5 T = 4/6 p1 = 0.5 T = 1/6 Observe that the formula, T = 2 p1 (1 – p1), is not correct. Copyright Agrawal, 2007
Copyright ELEC5270001/6270001 Jan 24 Lecture 3 25 Cause for Error and Correction Probability
Probability of transition is not independent of
the present state of the signal.
the Determine probability p 01 of a 0→1
Determine
transition.
transition. Recognize p 01 ≠ p 0 × p 1
Recognize We obtain p 1 = (1 – p 1) p 01 + p 1 p 11
We
11
p 01
01
p 1 = ─────────
─────────
1 – p 11 + p 01
01
Copyright Agrawal, 2007
Copyright ELEC5270001/6270001 Jan 24 Lecture 3 26 Correction (Cont.) Since
Since p 11 + p 10 = 1, i.e., given that the
signal was previously 1, its present value
can be either 1 or 0.
can Therefore,
p 01
01
p 1 = ──────
──────
p 10 + p 01
01
This uniquely gives signal probability as a
This
function of transition probabilities.
function
Copyright Agrawal, 2007
Copyright ELEC5270001/6270001 Jan 24 Lecture 3 27 Transition and Signal Probabilities
p01 = p10 = 1.0
p00 = p11 = 0.0 p1 = 0.5
1/fck p01 = p10 = 2/3
p00 = p11 = 1/3 p1 = 0.5 p01 = p10 = 1/4
p01 = p10 = 3/4 Copyright Agrawal, 2007
Copyright p1 = 0.5 ELEC5270001/6270001 Jan 24 Lecture 3 28 Probabilities: p0, p1, p00, p01, p10, p11 p 01 + p 00 = 1
00
p 11 + p 10 = 1
10
p0=1–p1
p 01
01
p 1 = ───────
───────
p 10 + p 01
01 Copyright Agrawal, 2007
Copyright ELEC5270001/6270001 Jan 24 Lecture 3 29 Transition Density
T = 2 p 1 (1 – p 1) = p 0 p 01 + p 1 p 10
10
= 2 p 10 p 01 / (p 10 + p 01)
01
01)
= 2 p 1 p 10 = 2 p 0 p 01
01 Copyright Agrawal, 2007
Copyright ELEC5270001/6270001 Jan 24 Lecture 3 30 Power Calculation Power
Power can be estimated if transition
density is known for all signals.
density Calculation of transition density requires Signal probabilities Transition densities for primary inputs;
Transition
computed from vector statistics
computed Copyright Agrawal, 2007
Copyright ELEC5270001/6270001 Jan 24 Lecture 3 31 Signal Probabilities
x1
x1 x2
x2
x1
x1 + x2 – x1x2
x2
1  x1 x1 Copyright Agrawal, 2007
Copyright ELEC5270001/6270001 Jan 24 Lecture 3 32 Signal Probabilities
x1
x2
x3
X1
0
0
0
0
1
1
1
1 0.5
x1 x2
0.25 0.5 0.625 0.5 X2
0
0
1
1
0
0
1
1
Copyright Agrawal, 2007
Copyright X3
0
1
0
1
0
1
0
1 Y
1
0
1
0
1
0
1
1 y = 1  ( 1  x1 x 2 ) x 3
= 1  x3 + x1x2x3
= 0.625
Ref: K. P. Parker and E. J. McCluskey,
“Probabilistic Treatment of General
Combinational Networks,” IEEE Trans.
on Computers, vol. C24, no. 6, pp. 668670, June 1975.
ELEC5270001/6270001 Jan 24 Lecture 3 33 Correlated Signal Probabilities
x1 0.5
x1 x2
0.5 0.25 x2 X1
0
0
1
1 X2
0
1
0
1 Copyright Agrawal, 2007
Copyright 0.625?
y = 1  (1  x1x2) x2
= 1 – x2 + x1x2x2
= 1 – x2 + x1x2
= 0.75 (correct value) Y
1
0
1
1 ELEC5270001/6270001 Jan 24 Lecture 3 34 Correlated Signal Probabilities
x1
x2 X1
0
0
1
1 0.5 x1 + x2 – x1x2 0.5 0.75 X2
0
1
0
1 Copyright Agrawal, 2007
Copyright 0.375? y = (x 1 + x 2 – x 1 x 2 ) x 2
= x1x2 + x2x2 – x1x2x2
= x1x2 + x2 – x1x2
= x2
= 0.5 (correct value) Y
0
1
0
1 ELEC5270001/6270001 Jan 24 Lecture 3 35 Observation Numerical
Numerical computation of signal
probabilities is accurate for fanoutfree
circuits.
circuits. Copyright Agrawal, 2007
Copyright ELEC5270001/6270001 Jan 24 Lecture 3 36 Remedies Use
Use Shannon’s expansion theorem to
compute signal probabilities.
compute Use Boolean difference formula to
Use
compute transition densities.
compute Copyright Agrawal, 2007
Copyright ELEC5270001/6270001 Jan 24 Lecture 3 37 Shannon’s Expansion Theorem C.
C. E. Shannon, “A Symbolic Analysis of Relay
and Switching Circuits,” Trans. AIEE, vol. 57,
Trans.
vol.
pp. 713723, 1938.
pp. Consider: Boolean variables, X1, X2, . . . , Xn Boolean function, F(X1, X2, . . . , Xn) Then F = Xi F(Xi=1) + Xi’ F(Xi=0) Where Xi’ is complement of X1 Cofactors, F(Xi=j) = F(X1, X2, . . , Xi=j, . . , Xn), j = 0 or 1
Copyright Agrawal, 2007
Copyright ELEC5270001/6270001 Jan 24 Lecture 3 38 Expansion About Two Inputs
F = XiXj F(Xi=1, Xj=1) + XiXj’ F(Xi=1, Xj=0)
XiXj
+ Xi’Xj F(Xi=0, Xj=1)
+ Xi’Xj’ F(Xi=0, Xj=0) In general, a Boolean function can be
In
expanded about any number of input
variables.
variables. Expansion about k variables will have 2k
terms.
terms. Copyright Agrawal, 2007
Copyright ELEC5270001/6270001 Jan 24 Lecture 3 39 Correlated Signal Probabilities
X1 X1 X2 Y = X1 X2 + X2’ X2 X1
0
0
1
1 X2
0
1
0
1 Copyright Agrawal, 2007
Copyright Y
1
0
1
1 Shannon expansion about the
reconverging input, X2:
Y = X2 Y(X2 = 1) + X2’ Y(X2 = 0)
= X2 (X1) + X2’ (1) ELEC5270001/6270001 Jan 24 Lecture 3 40 Correlated Signals When
When the output function is expanded about all
reconverging input variables,
reconverging All cofactors correspond to fanoutfree circuits. Signal probabilities for cofactor outputs can be calculated
Signal
without error.
without A weighted sum of cofactor probabilities gives the correct
weighted
probability of the output.
probability For two reconverging inputs: f = xixj f(Xi=1, Xj=1) + xi(1xj) f(Xi=1, Xj=0)
+ (1xi)xj f(Xi=0, Xj=1) + (1xi)(1xj) f(Xi=0, Xj=0)
Copyright Agrawal, 2007
Copyright ELEC5270001/6270001 Jan 24 Lecture 3 41 Correlated Signal Probabilities
X1 X1 X2 Y = X1 X2 + X2’ X2
X1
0
0
1
1 X2
0
1
0
1 Y
1
0
1
1 Shannon expansion about the
reconverging input, X2:
Y = X2 Y(X2=1) + X2’ Y(X2=0)
= X2 (X1) + X2’ (1)
y = x2 (0.5) + (1x2) (1)
= 0.5 (0.5) + (10.5) (1)
= 0.75 Copyright Agrawal, 2007
Copyright ELEC5270001/6270001 Jan 24 Lecture 3 42 Example
0.5
0.5
1
0
0.5
Reconv.
signal Supergate
0.25
0.5
0.0 Point of
reconv. 0.0 0.5
1.0 0.5
1.0
0.375 Signal probability for supergate output
= 0.5 Prob{rec. signal = 1} + 1.0 Prob{rec. signal = 0}
= 0.5 × 0.5 + 1.0 × 0.5 = 0.75 S. C. Seth and V. D. Agrawal, “A New Model for Computation of
Probabilistic Testability in Combinational Circuits,” Integration, the VLSI
Journal, vol. 7, no. 1, pp. 4975, April 1989.
Copyright Agrawal, 2007
Copyright ELEC5270001/6270001 Jan 24 Lecture 3 43 Probability Calculation Algorithm Partition circuit into supergates. Definition:
Definition: A supergate is a circuit partition with a single output
such that all fanouts that reconverge at the output are contained
within the supergate. Identify
Identify reconverging and nonreconverging inputs
of each supergate.
of Compute signal probabilities from PI to PO: For a supergate whose input probabilities are known Enumerate reconverging input states For each input state do gate by gate probability computation Sum up corresponding signal probabilities, weighted by state
Sum
probabilities
probabilities
Copyright Agrawal, 2007
Copyright ELEC5270001/6270001 Jan 24 Lecture 3 44 Calculating Transition Density .
.
.
.
. x1, T1 xn, Tn Copyright Agrawal, 2007
Copyright 1 Boolean
function y, T(Y) = ? n ELEC5270001/6270001 Jan 24 Lecture 3 45 Boolean Difference
Boolean diff(Y, Xi) = ∂Y
── = Y(Xi=1) ⊕ Y(Xi=0)
∂Xi Boolean diff(Y, Xi) = 1 means that a path is sensitized from input
Boolean
Xii to output Y.
X Prob(Boolean diff(Y, Xi) = 1) is the probability of transmitting a
Prob(Boolean
toggle from Xi to Y.
toggle Probability of Boolean difference is determined from the
Probability
probabilities of cofactors of Y with respect to Xi. F. F. Sellers, M. Y. Hsiao and L. W. Bearnson, “Analyzing Errors with
the Boolean Difference,” IEEE Trans. on Computers, vol. C17, no. 7,
pp. 676683, July 1968.
Copyright Agrawal, 2007
Copyright ELEC5270001/6270001 Jan 24 Lecture 3 46 Transition Density
n
T(y) = Σ T(Xi) Prob(Boolean diff(Y, Xi) = 1)
i=1 F. Najm, “Transition Density: A New Measure of Activity in Digital
Circuits,” IEEE Trans. CAD, vol. 12, pp. 310323, Feb. 1993. Copyright Agrawal, 2007
Copyright ELEC5270001/6270001 Jan 24 Lecture 3 47 Power Computation For each primary input, determine signal probability and
For
transition density for given vectors.
transition
For each internal node and primary output Y, find the
For
transition density T(Y), using supergate partitioning and
the Boolean difference formula.
the
Compute power,
P= Σ 0.5CY V2 T(Y) all Y
all
where CY is the capacitance of node Y and V is supply
voltage.
voltage.
Copyright Agrawal, 2007
Copyright ELEC5270001/6270001 Jan 24 Lecture 3 48 Transition Density and Power
X1
X2
X3 0.2, 1
0.3, 2 0.06, 0.7
0.436, 3.24 Ci
Y 0.4, 3 CY Transition density
Signal probability Power = 0.5 V 2 (0.7Ci + 3.24CY) Copyright Agrawal, 2007
Copyright ELEC5270001/6270001 Jan 24 Lecture 3 49 Prob. Method vs. Logic Sim.
Prob.
Circuit
Circuit No. of Probability method
Logic Simulation
No.
gates Av. density CPU s* Av. density CPU s*
gates Error
% C432 160 3.46 0.52 3.39 63 +2.1 C499 202 11.36 0.58 8.57 241 +29.8 C880 383 2.78 1.06 3.25 132 14.5 C1355 346 4.19 1.39 6.18 408 32.2 C1908 880 2.97 2.00 5.01 464 40.7 C2670 1193 3.50 3.45 4.00 619 12.5 C3540 1669 4.47 3.77 4.49 1082 0.4 C5315 2307 3.52 6.41 4.79 1616 26.5 25.10 5.67 34.17 31057 26.5 3.83 9.85 5.08 2713 24.2 C6288 2406
*C7552 3512
CONVEX c240
Copyright Agrawal, 2007
Copyright ELEC5270001/6270001 Jan 24 Lecture 3 50 Probability Waveform Methods F. Najm, R. Burch, P. Yang and I. Hajj, “CREST – A
F.
Current Estimator for CMOS Circuits,” Proc. IEEE Int.
Conf. on CAD, Nov. 1988, pp. 204207.
Conf.
C.S. Ding, et al., “GateLevel Power Estimation using
C.S.
et .,
Tagged Probabilistic Simulation,” IEEE Trans. on
CAD, vol. 17, no. 11, pp. 10991107, Nov. 1998.
CAD
F. Hu and V. D. Agrawal, “DualTransition Glitch
F.
Filtering in Probabilistic Waveform Power Estimation,”
Proc. IEEE Great Lakes Symp. VLSI, Apr. 2005, pp.
Proc.
Apr.
357360.
357360.
F. Hu and V. D. Agrawal, “Enhanced DualTransition
Enhanced
Probabilistic Power Estimation with Selective
Supergate Analysis,” Proc. IEEE Int. Conf. Computer
Design, Oct. 2005. pp. 366369.
Design Copyright Agrawal, 2007
Copyright ELEC5270001/6270001 Jan 24 Lecture 3 51 Problem 1
For equiprobable inputs analyze the 0→1 transition probabilities of all gates in the two implementations of a fourinput AND gate shown below. Assuming that the gates have zero delays, which implementation will consume less average dynamic power? E A
B
C
D F Chain structure Copyright Agrawal, 2007
Copyright G E A
B
C
D G F
Tree structure ELEC5270001/6270001 Jan 24 Lecture 3 52 Problem 1 Solution Given the primary input probabilities, P(A) = P(B) = P(C) = P(D) = 0.5, signal and transition (0→1) probabilities are as follows:
Signal
name Prob(sig.= 1) Prob(0→1) Prob(sig.=1) Prob(0→1) E 0.2500
0.1875 0.2500 0.1875 F 0.1250 0.1094 0.2500 0.1875 G 0.0625 0.0586 0.0625 0.0586 Total Chain Tree 0.3555 0.4336 transitions/vector The tree implementation consumes 100×(0.4336 – 0.3555)/0.3555 = 22% more average dynamic power. This advantage of the chain structure may be somewhat reduced because of glitches caused by unbalanced path delays.
Copyright Agrawal, 2007
Copyright ELEC5270001/6270001 Jan 24 Lecture 3 53 Problem 2
Assume that the twoinput AND gates in Problem 1 each has one unit of delay. Find input vector pairs for each implementation that will consume the peak dynamic power. Which implementation has lower peak dynamic power consumption? E A
B
C
D F Chain structure Copyright Agrawal, 2007
Copyright G E A
B
C
D G F
Tree structure ELEC5270001/6270001 Jan 24 Lecture 3 54 Problem 2 Solution
For the chain structure, a vector pair {A B C D} = {1110}, {1011} will produce four gate transitions as shown below. A E F B
C
D G A=11
B=10
E=10
C=11
F=10
D=01
G=00
0
Copyright Agrawal, 2007
Copyright 1 2 3 Time units ELEC5270001/6270001 Jan 24 Lecture 3 55 Problem 2 Solution (Cont.) The tree structure has balanced delay paths. So it cannot make more than 3 gate transitions. A vector pair {ABCD} = {1111},{1010} will produce three transitions as shown below. A E B G C
D F A=11 Therefore, just counting the gate transitions, we find that the chain consumes 100(4 – 3)/3 = 33% higher peak power than the tree. B=10
E=10
C=11
D=10
F=10
G=10 0 1 2 Copyright Agrawal, 2007
Copyright 3 Time units
ELEC5270001/6270001 Jan 24 Lecture 3 56 ...
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This note was uploaded on 09/17/2011 for the course ELEC 6970 taught by Professor Staff during the Spring '08 term at Auburn University.
 Spring '08
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