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Unformatted text preview: ELEC 5270/6270 Spring 2011
LowPower Design of Electronic Circuits GateLevel Power Optimization
GateLevel
Vishwani D. Agrawal James J. Danaher Professor
Dept. of Electrical and Computer Engineering
Auburn University, Auburn, AL 36849
[email protected]
http://www.eng.auburn.edu/~vagrawal/COURSE/E6270_Spr11/course.html
Copyright Agrawal, 2007
Copyright ELEC5270/6270 Spring 11, Lecture 5 1 Components of Power Dynamic Signal transitions Logic activity
Glitches Shortcircuit (often neglected) Static Leakage Copyright Agrawal, 2007
Copyright ELEC5270/6270 Spring 11, Lecture 5 2 Power of a Transition
isc R VDD Dynamic Power
Vo Vi = CLVDD2/2 + P sc CL R
Ground Copyright Agrawal, 2007
Copyright ELEC5270/6270 Spring 11, Lecture 5 3 Dynamic Power
transition of a gate consumes CV 2/2. Methods of power saving: Each
Each Minimize load capacitances Transistor sizing
Librarybased gate selection Reduce transitions Logic design
Glitch reduction Copyright Agrawal, 2007
Copyright ELEC5270/6270 Spring 11, Lecture 5 4 Glitch Power Reduction Design
Design a digital circuit for minimum transient
energy consumption by eliminating hazards
energy Copyright Agrawal, 2007
Copyright ELEC5270/6270 Spring 11, Lecture 5 5 Theorem 1 For
For correct operation with minimum energy
consumption, a Boolean gate must produce
no more than one event per transition.
one Output logic state changes
One transition is necessary Copyright Agrawal, 2007
Copyright Output logic state unchanged
No transition is necessary ELEC5270/6270 Spring 11, Lecture 5 6 Event Propagation
Single lumped inertial delay modeled for each gate
PI transitions assumed to occur without time skew
Path P1
1 0 13 P2 0 0 Copyright Agrawal, 2007
Copyright 2 1 3
2 246 Path P3
5 ELEC5270/6270 Spring 11, Lecture 5 7 Inertial Delay of an Inverter
Vin dHL+dLH dHL dLH d = ──── 2 Vout
time
Copyright Agrawal, 2007
Copyright ELEC5270/6270 Spring 11, Lecture 5 8 MultiInput Gate
A
DPD: Differential path delay Delay d < DPD C B A DPD B C
Copyright Agrawal, 2007
Copyright d d Hazard or glitch
ELEC5270/6270 Spring 11, Lecture 5 9 Balanced Path Delays
A DPD Delay buffer Delay
d < DPD C B A
B C
Copyright Agrawal, 2007
Copyright d No glitch
ELEC5270/6270 Spring 11, Lecture 5 10 Glitch Filtering by Inertia
A
Delay d > DPD C B A DPD B d > DPD C
Copyright Agrawal, 2007
Copyright Filtered glitch
ELEC5270/6270 Spring 11, Lecture 5 11 Theorem Given
Given that events occur at the input of a gate,
whose inertial delay is d, at times, t1 ≤ . . . ≤ tn ,
at
the number of events at the gate output cannot
exceed
exceed
t –t
n 1 min ( n , 1 + ────
min
d ) tn  t 1 t1
Copyright Agrawal, 2007
Copyright t2 t3 tn ELEC5270/6270 Spring 11, Lecture 5 time
time 12 Minimum Transient Design Minimum
Minimum transient energy condition for a
Boolean gate:
Boolean
 ti – tj  < d Where ti and tj are arrival times of input
Where
events and d is the inertial delay of gate Copyright Agrawal, 2007
Copyright ELEC5270/6270 Spring 11, Lecture 5 13 Balanced Delay Method All input events arrive simultaneously
Overall circuit delay not increased
Delay buffers may have to be inserted
1 1 1 1 1 1 1 3 1 Copyright Agrawal, 2007
Copyright 1 1 ELEC5270/6270 Spring 11, Lecture 5 No increase in critical path delay 14 Hazard Filter Method Gate delay is made greater than maximum input
Gate
path delay difference
path
No delay buffers needed (least transient energy)
No
(least
Overall circuit delay may increase
1 1 1 1 1 Copyright Agrawal, 2007
Copyright 1 1 1 1 3 ELEC5270/6270 Spring 11, Lecture 5 15 Designing a GlitchFree Circuit Maintain specified critical path delay.
Glitch suppressed at all gates by Path delay balancing Glitch filtering by increasing inertial delay of gates or by
Glitch
inserting delay buffers when necessary.
inserting
A linear program optimally combines all objectives.
Path delay = d1
Path delay = d2 Copyright Agrawal, 2007
Copyright Delay
D ELEC5270/6270 Spring 11, Lecture 5 d1 – d2 < D 16 Problem Complexity Number
Number of paths in a circuit can be
exponential in circuit size.
exponential Considering all paths through enumeration
is infeasible for large circuits.
is Example: Copyright Agrawal, 2007
Copyright c880 has 6.96M path constraints. ELEC5270/6270 Spring 11, Lecture 5 17 Define Arrival Time Variables di Gate delay.
Gate Define two timing window variables per gate output:
Define Earliest time of signal transition at gate i. ti
Ti Latest time of signal transition at gate i. Glitch suppression constraint: Ti – ti < di
Glitch
t1, T1
ti, Ti
.
.
. di tn, Tn
Reference: T. Raja, Master’s Thesis, Rutgers Univ., 2002.
Copyright Agrawal, 2007
Copyright ELEC5270/6270 Spring 11, Lecture 5 18 Linear Program Variables:
Variables: gate and buffer delays,
arrival time variables.
arrival Objective: minimize number of buffers. Subject to: overall circuit delay
Subject
constraint for all inputoutput paths.
constraint Subject to: minimum transient energy
Subject
condition for all multiinput gates.
condition
Copyright Agrawal, 2007
Copyright ELEC5270/6270 Spring 11, Lecture 5 19 An Example: Full Adder add1b
1
1 1 1
1 1 1
1 1
Critical path delay = 6 Copyright Agrawal, 2007
Copyright ELEC5270/6270 Spring 11, Lecture 5 20 Linear Program Gate variables: d4 . . . d12 Buffer delay variables: d15 . . . d29
15 Window variables: t4 . . . t29 and T4 . . . . T29
Copyright Agrawal, 2007
Copyright ELEC5270/6270 Spring 11, Lecture 5 21 MultipleInput Gate Constraints For Gate 7:
For
T7 ≥ T5 + d7 t7 ≤ t5 + d7 d7 > T7 – t7 T7 ≥ T6 + d7 t7 ≤ t6 + d7 Glitch suppression
Glitch Copyright Agrawal, 2007 ELEC5270/6270 Spring 11, Lecture 5 22 SingleInput Gate Constraints Buffer 19: T16 + d19 = T19
t16 + d19 = t19 Copyright Agrawal, 2007
Copyright ELEC5270/6270 Spring 11, Lecture 5 23 Critical Path Delay Constraints T11 ≤ maxdelay
maxdelay
T12 ≤ maxdelay
maxdelay
maxdelay is specified
Copyright Agrawal, 2007
Copyright ELEC5270/6270 Spring 11, Lecture 5 24 Objective Function
Objective Need to minimize the number of buffers. Because that leads to a nonlinear
Because
objective function, we use an approximate
criterion:
criterion:
minimize ∑ (buffer delay)
minimize (buffer
all buffers
all i.e., This minimize d15 + d16 + ∙ ∙ ∙ + d29
minimize
gives a near optimum result. Copyright Agrawal, 2007 ELEC5270/6270 Spring 11, Lecture 5 25 AMPL Solution: maxdelay = 6
AMPL
1 1 2 1 1
2 1 1
1 2 2
Critical path delay = 6 Copyright Agrawal, 2007
Copyright ELEC5270/6270 Spring 11, Lecture 5 26 AMPL Solution: maxdelay = 7
AMPL
3
1 1 1
2 1 1
2 1 2
Critical path delay = 7 Copyright Agrawal, 2007
Copyright ELEC5270/6270 Spring 11, Lecture 5 27 AMPL Solution: maxdelay ≥ 11
AMPL
11
5
1 1 1
2 3 1
3 4
Critical path delay = 11 Copyright Agrawal, 2007
Copyright ELEC5270/6270 Spring 11, Lecture 5 28 ALU4: FourBit ALU 74181
maxdelay Buffers inserted 7
10
12
15 5
2
1
0 Maximum Power Savings (zerobuffer design):
Peak = 33%, Average = 21%
Copyright Agrawal, 2007
Copyright ELEC5270/6270 Spring 11, Lecture 5 29 ALU4: Original and LowPower Copyright Agrawal, 2007
Copyright ELEC5270/6270 Spring 11, Lecture 5 30 Benchmark Circuits
Normalized Power
Average
Peak Circuit Maxdelay
(gates) No. of
Buffers ALU4 7
15 5
0 0.80
0.79 0.68
0.67 C880 24
48 62
34 0.68
0.68 0.54
0.52 C6288 47
94 294
120 0.40
0.36 0.36
0.34 c7552 43
86 366
111 0.44
0.42 0.34
0.32 Copyright Agrawal, 2007
Copyright ELEC5270/6270 Spring 11, Lecture 5 31 C7552 Circuit: Spice Simulation Power Saving: Average 58%, Peak 68%
Copyright Agrawal, 2007
Copyright ELEC5270/6270 Spring 11, Lecture 5 32 References R. Fourer, D. M. Gay and B. W. Kernighan, AMPL: A Modeling Language for
R.
Mathematical Programming, South San Francisco: The Scientific Press, 1993.
Mathematical
M. Berkelaar and E. Jacobs, “Using Gate Sizing to Reduce Glitch Power,” Proc.
M.
ProRISC Workshop, Mierlo, The Netherlands, Nov. 1996, pp. 183188.
ProRISC
V. D. Agrawal, “Low Power Design by Hazard Filtering,” Proc. 10th Int’l Conf.
V.
10
VLSI Design, Jan. 1997, pp. 193197.
VLSI
V. D. Agrawal, M. L. Bushnell, G. Parthasarathy and R. Ramadoss, “Digital
V.
Circuit Design for Minimum Transient Energy and Linear Programming Method,”
Proc. 12th Int’l Conf. VLSI Design, Jan. 1999, pp. 434439.
12
T. Raja, V. D. Agrawal and M. L. Bushnell, “Minimum Dynamic Power CMOS
Circuit Design by a Reduced Constraint Set Linear Program,” Proc. 16th Int’l
Proc.
Conf. VLSI Design, Jan. 2003, pp. 527532.
Conf.
T. Raja, V. D. Agrawal, and M. L. Bushnell, “Transistor sizing of logicgates to
T.
maximize input delay variability,” J. Low Power Electron., vol.2, no. 1, pp. 121–
J.
128, Apr. 2006.
T. Raja, V. D. Agrawal, and M. L. Bushnell, “Variable Input Delay CMOS Logic
T.
for Low Power Design,” IEEE Trans. VLSI Design, vol. 17, mo. 10, pp. 1534for
1545. October 2009.
Copyright Agrawal, 2007
Copyright ELEC5270/6270 Spring 11, Lecture 5 33 Exercise: Dynamic Power
Exercise: An average gate VDD, V = 1 volt Output capacitance, C = 1pF Activity factor, α = 10%
Activity Clock frequency, f = 1GHz What
What is the dynamic power consumption
of a 1 million gate VLSI chip?
of Copyright Agrawal, 2007 ELEC5270/6270 Spring 11, Lecture 5 34 Answer
Answer Dynamic energy per transition = 0.5CV2 Dynamic power per gate
= Energy per second
= 0.5 CV2 α f
= 0.5 ✕ 10 – 12 ✕ 12 ✕ 0.1 ✕ 109
= 0.5 ✕ 10 – 4 = 50μW Power for 1 million gate chip = 50W
Copyright Agrawal, 2007 ELEC5270/6270 Spring 11, Lecture 5 35 Components of Power Dynamic Signal transitions Logic activity
Glitches Shortcircuit Static Leakage Copyright Agrawal, 2007
Copyright ELEC5270/6270 Spring 11, Lecture 5 36 Subthreshold Conduction
Ids Vgs – Vth
–Vds
I0 exp( ───── ) × (1– exp ─── )
nVT
VT = 1mA
100μA
10μA
1μA
100nA
10nA
1nA
100pA
10pA Copyright Agrawal, 2007
Copyright Subthreshold
region Ids
Saturation region g
Subthreshold slope d
s Vth
0 0.3 0.6 0.9 1.2 ELEC5270/6270 Spring 11, Lecture 5 1.5 1.8 V Vgs
37 Thermal Voltage, vT
Thermal
VT = kT/q = 26 mV, at room temperature.
When Vds is several times greater than VT Ids Copyright Agrawal, 2007
Copyright = Vgs – Vth
I0 exp( ───── )
nVT
ELEC5270/6270 Spring 11, Lecture 5 38 Leakage Current Leakage
Leakage current equals Ids when Vgs = 0
gs Leakage
Leakage current, Ids = I0 exp( – Vth/nVT) At
At cutoff, Vgs = Vtth , and Ids = I0
h Lowering leakage to 10b ✕ I0 Vth = bnVT ln 10 = 1.5b × 26 ln 10 = 90b mV
bnV ln
26 Example:
Example: To lower leakage to I0/1,000
Vth = 270 mV Copyright Agrawal, 2007
Copyright ELEC5270/6270 Spring 11, Lecture 5 39 Threshold Voltage Vth = Vt0 + γ[(Φs+Vsb)½ – Φs½] Vt0 is threshold voltage when source is at
body potential (0.4 V for 180nm process)
body Φs = 2VT ln(NA /ni ) is surface potential
ln( /n is
γ = (2qεsi NA)½tox /εox is body effect
si
ox
coefficient (0.4 to 1.0)
coefficient NA is doping level = 8×1017 cm–3 ni = 1.45×1010 cm–3 Copyright Agrawal, 2007
Copyright ELEC5270/6270 Spring 11, Lecture 5 40 Threshold Voltage, Vsb = 1.1V
Threshold
1.1V
sb Thermal
Thermal voltage, VT = kT/q = 26 mV
kT/q Φs = 0.93 V εox = 3.9×8.85×1014 F/cm εsi = 11.7×8.85×1014 F/cm tox = 40 Ao γ = 0.6 V½ Vth = Vt0 + γ[(Φs+Vsb)½ Φs½] = 0.68 V Copyright Agrawal, 2007
Copyright ELEC5270/6270 Spring 11, Lecture 5 41 A Sample Calculation VDD = 1.2V, 100nm CMOS process Transistor width, W = 0.5μm OFF device (Vgs = Vth) leakage
I0 = 20nA/μm, for low threshold transistor
I0 = 3nA/μm, for high threshold transistor 100M transistor chip Power = (100×106/2)(0.5×20×109A)(1.2V) = 600mW for
A)(1.2V)
all lowthreshold transistors
all
Power = (100×106/2)(0.5×3×109A)(1.2V) = 90mW for
A)(1.2V)
all highthreshold transistors
all
Copyright Agrawal, 2007
Copyright ELEC5270/6270 Spring 11, Lecture 5 42 DualThreshold Chip Lowthreshold
Lowthreshold only for 20% transistors on critical path.
critical Leakage power
Leakage Copyright Agrawal, 2007
Copyright =
=
= 600×0.2 + 90×0.8
600×0.2
120 + 72
192 mW ELEC5270/6270 Spring 11, Lecture 5 43 DualThreshold CMOS Circuit Copyright Agrawal, 2007
Copyright ELEC5270/6270 Spring 11, Lecture 5 44 DualThreshold Design To maintain performance, all gates on
To
critical paths are assigned low Vtth .
h Most other gates are assigned high Vtth .
Most
h But, some gates on noncritical paths
But,
may also be assigned low Vth to prevent
those paths from becoming critical.
those Copyright Agrawal, 2007
Copyright ELEC5270/6270 Spring 11, Lecture 5 45 Integer Linear Programming (ILP) to
Integer
Minimize Leakage Power
Minimize Use dualthreshold CMOS process First, assign all gates low Vth
First, Use an ILP model to find the delay (Tc) of the
of
critical path
critical Use another ILP model to find the optimal Vth
Use
assignment as well as the reduced leakage
power for all gates without increasing Tc Further
Further reduction of leakage power possible
by letting Tc increase Copyright Agrawal, 2007
Copyright ELEC5270/6270 Spring 11, Lecture 5 46 ILP Variables
For each gate i define two variables. Ti : the longest time at which the output of
gate i can produce an event after the
occurrence of an input event at a primary
input of the circuit. Xi : a variable specifying low or high Vth
variable
for gate i ; Xi is an integer [0, 1],
1 gate i is assigned low Vtth ,
h
0 gate i is assigned high Vtth .
h
Copyright Agrawal, 2007
Copyright ELEC5270/6270 Spring 11, Lecture 5 47 ILP  objective function
ILP objective
Leakage power: Pleak = Vdd ∑ I leaki
i minimize the sum of all gate leakage currents, given by Min∑ ( X i ⋅ I Li + (1 − X i ) ⋅ I Hi )
i ILi is the leakage current of gate i with low Vth
Li
IHi is the leakage current of gate i with high Vth
Using SPICE simulation results, construct a leakage
Using
current look up table, which is indexed by the gate
type and the input vector.
type Copyright Agrawal, 2007
Copyright ELEC5270/6270 Spring 11, Lecture 5 48 ILP  Constraints
ILP Constraints For each gate
For
(1)
(1) Gate i Ti ≥ T j + X i ⋅ DLi + (1 − X i ) ⋅ DHi Ti output of gate j is fanin of gate i
output
(2) Gate j 0 ≤ Xi ≤1 Tj Max delay constraints for primary outputs (PO)
Max
(3) Ti ≤ Tmax
Tmax is the maximum delay of the critical path Copyright Agrawal, 2007
Copyright ELEC5270/6270 Spring 11, Lecture 5 49 ILP Constraint Example
0 1 2
3 Ti ≥ T j + X i ⋅ DLi + (1 − X i ) ⋅ DHi Assume all primary input (PI) signals on the left arrive at the
Assume
same time.
For gate 2, constraints are T2 ≥ T0 + X 2 ⋅ DL 2 + (1 − X 2 ) ⋅ DH 2 T2 ≥ 0 + X 2 ⋅ DL 2 + (1 − X 2 ) ⋅ DH 2
Copyright Agrawal, 2007
Copyright ELEC5270/6270 Spring 11, Lecture 5 50 ILP – Constraints (cont.) DHi is
Hi is the delay of gate i with high Vth
with DLi is
Li is the delay of gate i with low Vth
with A second lookup table is constructed and
second
specifies the delay for given gate types
and fanout numbers. Copyright Agrawal, 2007
Copyright ELEC5270/6270 Spring 11, Lecture 5 51 ILP – Finding Critical Delay
Ti ≤ Tmax T can be specified or be the delay of longest path (Tc).
can To find Tc , we first delete the above constraint and assign
To
all gates low Vth max 0 ≤ Xi ≤1 Xi =1 Maximum Ti in the ILP solution is Tc.
Maximum If we replace T with Tc , the objective function then
If
minimizes leakage power without sacrificing performance.
minimizes Copyright Agrawal, 2007
Copyright max ELEC5270/6270 Spring 11, Lecture 5 52 PowerDelay Tradeoff
1
0.9 N
ormalized Leakage Pow
er 0.8
C
432
0.7
C
880
0.6 C
1908 0.5
0.4
0.3
0.2
0.1
1 1.1 1.2 1.3 1.4 1.5 N
ormalized C
ritical Path D
elay
Copyright Agrawal, 2007
Copyright ELEC5270/6270 Spring 11, Lecture 5 53 PowerDelay Tradeoff If
If we gradually increase Tmax from Tc , leakage
power is further reduced, because more gates
can be assigned high Vtth .
h But, the reduction trends to become slower. When Tmax = (130%) Tc , the reduction about
When max (130%)
levels off because almost all gates are
assigned high Vtth .
h Maximum
Maximum
Copyright Agrawal, 2007
Copyright leakage reduction can be 98%.
ELEC5270/6270 Spring 11, Lecture 5 54 Leakage & Dynamic Power Optimization 70nm
Leakage
CMOS c7552 Benchmark Circuit @ 90oC
CMOS
900
700
600
500
400
300
200
100
0 Leakage power
Dynam ic power
Tot al power Le
ex aka d cee ge
yn d
po am s
we ic
r Micr owat t s 800 Or iginal cir cuit Copyright Agrawal, 2007
Copyright Opt im ized
design
ELEC5270/6270 Spring 11, Lecture 5 Y. Lu and V. D. Agrawal, “CMOS Leakage and Glitch Minimization for PowerPerformance Tradeoff,” Journal of Low Power Electronics (JOLPE), vol. 2, no. 3, pp. 378387, December 2006. 55 Summary Leakage
Leakage power is a significant fraction of the
total power in nanometer CMOS devices.
total Leakage power increases with temperature; can
Leakage
be as much as dynamic power.
be Dual threshold design can reduce leakage. Reference: Y. Lu and V. D. Agrawal, “CMOS Leakage
and Glitch Minimization for PowerPerformance
Tradeoff,” J. Low Power Electronics, Vol. 2, No. 3, pp.
378387, December 2006. Access other paper at
http://www.eng.auburn.edu/~vagrawal/TALKS/talks.html
Copyright Agrawal, 2007
Copyright ELEC5270/6270 Spring 11, Lecture 5 56 Problem: Leakage Reduction
Following circuit is designed in 65nm CMOS technology using low threshold transistors. Each gate has a delay of 5ps and a leakage current of 10nA. Given that a gate with high threshold transistors has a delay of 12ps and leakage of 1nA, optimally design the circuit with dualthreshold gates to minimize the leakage current without increasing the critical path delay. What is the percentage reduction in leakage power? What will the leakage power reduction be if a 30% increase in the critical path delay is allowed? Copyright Agrawal, 2007
Copyright ELEC5270/6270 Spring 11, Lecture 5 57 Solution 1: No Delay Increase Three critical paths are from the first, second and third inputs to the last output, shown by a dashed line arrow. Each has five gates and a delay of 25ps. None of the five gates on the critical path (red arrow) can be assigned a high threshold. Also, the two inverters that are on fourgate long paths cannot be assigned high threshold because then the delay of those paths will become 27ps. The remaining three inverters and the NOR gate can be assigned high threshold. These gates are shaded blue in the circuit.
The reduction in leakage power = 1 – (4×1+7×10)/(11×10) = 32.73%
Critical path delay = 25ps 12ps
5ps
12ps 5ps
5ps 5ps 12ps
12ps
Copyright Agrawal, 2007
Copyright ELEC5270/6270 Spring 11, Lecture 5 5ps
5ps
5ps
58 Solution 2: 30% Delay Increase Several solutions are possible. Notice that any 3gate path can have 2 high threshold gates. Four and five gate paths can have only one high threshold gate. One solution is shown in the figure below where six high threshold gates are shown with shading and the critical path is shown by a dashed red line arrow.
The reduction in leakage power = 1 – (6×1+5×10)/(11×10) = 49.09%
Critical path delay = 29ps
5ps 12ps
5ps 12ps
5ps 12ps 12ps
12ps
Copyright Agrawal, 2007
Copyright ELEC5270/6270 Spring 11, Lecture 5 12ps
5ps
5ps
59 ...
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This note was uploaded on 09/17/2011 for the course ELEC 6970 taught by Professor Staff during the Spring '08 term at Auburn University.
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