Unformatted text preview: ELEC 5270/6270 Spring 2011
LowPower Design of Electronic Circuits Test Power
Test
Vishwani D. Agrawal James J. Danaher Professor
Dept. of Electrical and Computer Engineering
Auburn University, Auburn, AL 36849
[email protected]
http://www.eng.auburn.edu/~vagrawal/COURSE/E6270_Spr11/course.html
Copyright Agrawal, 2007
Copyright ELEC6270 Spring 11, Lecture 6 1 Power Considerations in Design
A circuit is designed for certain function. Its design
circuit
must allow the power consumption necessary to
execute that function.
execute Power buses are laid out to carry the maximum
Power
current necessary for the function.
current Heat dissipation of package conforms to the
Heat
average power consumption during the intended
function.
function. Layout design and verification must account for
Layout
“hot spots” and “voltage droop” – delay, coupling
noise, weak signals.
noise,
Copyright Agrawal, 2007
Copyright ELEC6270 Spring 11, Lecture 6 2 Testing Differs from Functional
Testing
Operation
Operation
Other chips System
inputs System
outputs VLSI chip
system Functional inputs Copyright Agrawal, 2007
Copyright Functional outputs ELEC6270 Spring 11, Lecture 6 3 Basic Mode of Testing
Packaged or unpackaged
device under test (DUT) DUT output for
comparison with
expected response
stored in ATE VLSI chip
Test vectors:
Pregenerated
and stored in
ATE Copyright Agrawal, 2007
Copyright Clock Power Automatic Test Equipment (ATE):
Control processor, vector memory,
timing generators, power module,
response comparator
ELEC6270 Spring 11, Lecture 6 4 Functional Inputs vs. Test Vectors Functional inputs: Functionally
Functionally Test meaningful signals
signals Generated by circuitry Restricted set of inputs May
May have been
optimized to reduce
logic activity and power
logic Copyright Agrawal, 2007
Copyright ELEC6270 Spring 11, Lecture 6 vectors: Functionally
Functionally irrelevant signals
signals Generated by software
Generated
to test modeled faults
to Can be random or
Can
pseudorandom
pseudorandom May be optimized to
May
reduce test time; can
have high logic activity
have May use testability logic
May
for test application
for
5 An Example
VLSI chip in system operation 3bit random
vectors Binary to
decimal
converter 8bit
1hot
VLSI chip
vectors
system VLSI chip under test
High activity
8bit
test vectors
from ATE Copyright Agrawal, 2007
Copyright VLSI chip ELEC6270 Spring 11, Lecture 6 6 Comb. Circuit Power Optimization Given a set of test vectors Reorder vectors to minimize the number of
Reorder
transitions at primary inputs
transitions
01010101
00110011
00001111
11 transitions Combinational circuit
(tested by exhaustive
vectors) 01111000
Rearranged vector set 00110011
00011110
Copyright Agrawal, 2007
Copyright produces 7 transitions ELEC6270 Spring 11, Lecture 6 7 Reducing Comb. Test Power
Reducing
Original tests:
V1 V2 V3 V4 V5
11 00 0
10 10 0
10 10 1
10 11 1
10 input transitions
Reordered tests:
V1 V3 V5 V4 V2
10 00 1
11 00 0
11 10 0
11 11 0
5 input transitions
Copyright Agrawal, 2007
Copyright 1
V1 3 3 2
V4 4 V2
2
1 3 V3
1 V5
2 Traveling salesperson problem (TSP)
finds the shortest distance closed path
(or cycle) to visit all nodes exactly once.
But, we need an open loop solution. ELEC6270 Spring 11, Lecture 6 8 OpenLoop TSP
OpenLoop
1 0 3 V1
0 0 2 3 V0
0 V4 4 V2
2
1 3
V5 V3
1
2 0 Add a node V0 at distance 0 from all other nodes. Solve TSP for the new graph. Delete V0 from the solution.
Copyright Agrawal, 2007
Copyright ELEC6270 Spring 11, Lecture 6 9 Combinational Vector Ordering
Combinational TSP has exponential complexity; good heuristics are
TSP
available.
available.
For other extensions: V. Dabholkar, S. Chakravarty, I Pomeranz and S.
V.
Reddy, “Techniques for Minimizing Power Dissipation
in Scan and Combinational Circuits During Test
Application,” IEEE Trans. CAD, vol. 17, no. 12, pp.
IEEE
vol.
13251333, Dec. 1998.
13251333,
Typical average power saving: 3050% 5060% with vector repetition (to satisfy peak power) ? ? ? With inserted vectors (to satisfy peak power) Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 6 10 Traveling Salesperson Problem A.
A. V. Aho, J. E. Hopcroft anf J. D. Ullman, Data
Structures and Algorithms, Reading,
Structures
Reading,
Massachusetts: AddisonWesley, 1983.
Massachusetts: E. Horowitz and S. Sahni, Fundamentals of
E.
Computer Algorithms, Computer Science Press,
Computer
Computer
1984.
1984. B. R. Hunt, R. L. Lipsman, J. M. Rosenberg, K.
B.
R. Coombes, J. E. Osborn and G. J. Stuck, A
Guide to MATLAB for Beginners and
Experienced Users, Cambridge University
Experienced
Cambridge
Press, 2006.
Press,
Copyright Agrawal, 2007
Copyright ELEC6270 Spring 11, Lecture 6 11 Example: Branch and Bound
Method
Method A combinational circuit is tested by a set of five vectors.
combinational
The test system initializes to the first vector 0000, which
should be retained as the starting vector. Remaining
vectors can be arbitrarily sequenced. Find the minimum
energy test sequence. How much does your sequence
save over the original sequence? The given test vector
sequence is:
sequence
Vector number Copyright Agrawal, 2007 1
0
0
0
0 2
1
1
1
1 ELEC6270 Spring 11, Lecture 6 3
1
0
0
0 4
0
1
1
0 5
1
0
0
1
12 Begin with a Greedy Solution
Begin
Designated start 1 2 2 5
1 4 2
1 1 4 Copyright Agrawal, 2007 4 2 3 ELEC6270 Spring 11, Lecture 6 3 3
13 Branch and Bound Search
Branch
Slack = 6 1 Edge weight = 4 2 1 2 Slack = 2 2
3 3 2 4 3
2 5 3 4 Slack S = 0 S = 0
=–1
Terminate search when slack ≤ 0
Copyright Agrawal, 2007 1 3 2 5 4
5
4 4 ELEC6270 Spring 11, Lecture 6 All searches terminate
before reaching leaf
node. Minimum path
length = 6 2 2
2 4 Greedy path
Length = 6 14 C6288: Test Vector Ordering
C6288:
Paul Wray, “Minimize Test Power for Benchmark Circuit
c6288 by Optimal Ordering of Vectors,” Class Project,
ELEC 5270, Spring 2009.
PowerPoint Presentation and Report:
www.eng.auburn.edu/~vagrawal/COURSE/E6270_Spr09/course.html Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 6 15 Scan Testing
Primary
inputs Primary
outputs Combinational
logic Scanout
SO Scan enable
SE
Scanin
SI
Copyright Agrawal, 2007
Copyright Scan
flipflops D
D
SI 1
0 SO
mux D’ DFF D’ SE
ELEC6270 Spring 11, Lecture 6 16 Some Properties of Scan Testing
Some Two modes of operation: Normal mode
Scan mode Threestep test application: Scanin: sets inputs of logic in scan mode.
Capture: captures logic outputs in normal mode.
Scanout: observes captured outputs in scan
Scanout:
mode.
mode. Tests
Tests are nonfunctional; some tests may
consume excess power and could have been
intentionally avoided in functional mode.
intentionally Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 6 17 Example: State Machine
Functional transitions
Functional state
transitions S4
State encoding
S1 = 000
S2 = 001
S3 = 010
S4 = 011
S5 = 100 1
1 001 → 011 1
2 011 → 000 2 100 → 011 3 (Peak) Av. transitions S3 000 → 010 010 → 001 S2 Comb. State input
Comb.
changes/clock
changes/clock 000 → 100 S5 Copyright Agrawal, 2007
Copyright State transition S1 1.667 ELEC6270 Spring 11, Lecture 6 18 Reduced Power Design
Reduced
Functional transitions
Functional state
transitions S4 S1
S2 S3 Reduced power state encoding
S1 = 000
S2 = 011
S3 = 001
S4 = 010
S5 = 100
Copyright Agrawal, 2007
Copyright Comb. State input
Comb.
changes/clock
changes/clock 000 → 001 1 000 → 100 S5 State transition 1 011 → 010 1 001 → 011 1 010 → 000 1 100 → 010 2 (Peak) Av. transitions 1.167 (– 30%) ELEC6270 Spring 11, Lecture 6 19 Scan Testing: Shiftin, Shiftout
Primary
inputs Combinational
logic Primary
outputs Scanout
100 Scanin
010 Shiftout transition FF=1
Shiftin transition 100 → 010 2 010 → 101 FF=0
FF=0 Scan transitions
State
Per clock
State
Per
transition
state
transition
changes
changes 3 101 → 010 3 All
All
transitions
transitions 8 Shiftin transitions = Σ (scan chain length – position of transition)
Shiftout transitions = Σ (position of transition)
Copyright Agrawal, 2007
Copyright ELEC6270 Spring 11, Lecture 6 20 Scan Testing: Capture
Primary
inputs
1
0 1 Primary
1 outputs Combinational
logic FF=0
FF=1
FF=0 Copyright Agrawal, 2007
Copyright 1
0 Capture transitions: 3
Note that 101 is not a
functional state in the
reduced power state
encoding. 1 ELEC6270 Spring 11, Lecture 6 21 A Four FlipFlop Example
Four
01010
10100
01000
10000
10 transitions Combinational
Logic Scanout
F4 0
F3 0
F2 0
F1 0 0101
Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 6 22 Change Scan Chain Order
Change
00000
11000
00000
10000
2 transitions Combinational
Logic F4 0 Scanout F3 0
F2 0
1100 Copyright Agrawal, 2007 F1 0
ELEC6270 Spring 11, Lecture 6 23 0
1
0
1 1
0
1
1 Combinational
Logic F4 1 Output vector Input vector Capture Power
Capture 3 transitions
Scanout F3 0
F2 1
Next vector states Copyright Agrawal, 2007 F1 0
ELEC6270 Spring 11, Lecture 6 24 0
1
0
1 1
0
1
1 Combinational
Logic F4 1 Output vector Input vector Vector Order  Select Next Vector
Vector 3 transitions
Scanout F3 1
Next vector states
1111 or 1100 or 0011
Select 1100
Copyright Agrawal, 2007 F2 0 Captured response F1 1
ELEC6270 Spring 11, Lecture 6 25 Dynamic Power of Scan Test
Dynamic Capture
A power can be reduced: vector generation problem Shiftin
Shiftin and shiftout power is reduced by
vector ordering and scan chain ordering
scan Construct
Construct a flipflop node graph; edges weighted with
shift in/shift out activity
shift Find shortest distance Hamiltonian paths between all
Find
node pairs
node Select the path that minimizes shift power Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 6 26 Shiftin and Shiftout Matrices
Shiftin
N Scan flipflops: F1 through FN; M vectors: V1 through VM
F1 → F2 · → · Fj· → ·Fk · → · FN F1 → F2 · → · Fj · → · Fk · → · FN V1 0 1 ··· 1 ··· 0 ··· 1 1 1 ··· 1 ··· 0 ··· 0 V2 1 1 ··· 0 ··· 0 ··· 0 0 1 ··· 1 ··· 1 ··· 0 ··· ··· ··· ···
Ij
··· ··· ··· ··· ··· ··· ··· ··· ··· ··· ··· ··· ··· ··· ··· ··· Ik
··· ··· ··· ···
Oj
··· ··· ··· ··· ··· 1 0 ··· ··· VM 0 0 ··· 1 ··· 1 ··· 0
Flipflop states for test input ···
Ok
··· ··· ··· 0 ··· 0
···
Test output states 1 27
Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 6 A Complete Graph
Complete
wjk = Hamming(Ij, Ik) + Hamming(Oj, Ok)
w12
F1
F2
w
13 w16 w24 w23 w26
w15 F6 w14 w25
F3 w36 w46 w35 w56 w34
F5 F4
w45 Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 6 28 Graph Solutions for Scan Power
Graph High complexity of Hamiltonian path finding requires use of
High
heuristics.
heuristics.
Average power saving: ~3050% logic, ~1020% flipflops.
Average
Y. Bonhomne, P. Girard, Landrault, and S. C.
Y.
Pravossoudovtich, “Power Driven Chaining of Flip Flops in
Scan Architectures,” Proc. International Test Conf., 2002,
Proc.
.,
pp. 796–803.
pp.
Y. Bonhomne, P. Girard, L. Guiller, Landrault, and S. C.
Y.
Pravossoudovtich, “PowerDriven RoutingConstrained
Scan Chain Design,” J. Electronic Testing: Theory and
Applications, vol. 20, no. 6, pp. 647–660, Dec. 2004.
vol. Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 6 29 Low Power Scan FlipFlop
with Gated Data
SO SO SI
SE
CK D’
DFF SI 1 mux D mux D 0 D’
DFF CK
SE
SFF: Scan FF cell Copyright Agrawal, 2007
Copyright SFFGD: Gated data scan FF cell ELEC6270 Spring 11, Lecture 6 30 Low Power Scan FlipFlop
with Gated Clock and Data
SO SI 1 mux D 0 D’
DFF CK
SE
SFFGCKD: Gated clock and data scan FF cell Copyright Agrawal, 2007
Copyright ELEC6270 Spring 11, Lecture 6 31 s5378: Normal Mode Operation
s5378: 1,000 random vectors Clock period = 50ns Technology: TSMC025
FF cell No. of
used gates Dynamic power (μW)
Logic Glitch Dyn. Sh.Ck. Leak.
(μW) Clock
(μW) FF
(μW) Total
(μW) FF 2958 77.9 17.5 95.4 14.1 0.129 220.3 751.6 1081.5 SFF 3137 81.8 19.5 101.3 13.9 0.130 220.3 751.7 1087.3 SFFGD 3317 85.1 19.8 104.9 15.0 0.132 220.3 751.7 1091.9 SFFGCKD 3675 89.9 56.8 146.7 23.9 0.136 118.8 33.2 322.7 Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 6 32 s5378: Scan Test
s5378: Mentor
Mentor Graphics Fastscan, 98.9%
coverage
coverage Clock period = 50ns Technology: TSMC025
FF cell No. of
used gates Dynamic power (μW)
Logic Glitch Dyn. Sh.Ck. Leak.
(μW) Clock
(μW) FF
(μW) Total
(μW) SFF 3137 356.8 60.4 417.2 26.2 0.146 220.3 848.5 1512.4 SFFGD 3317 93.5 33.6 127.2 7.7 0.150 220.3 850.7 1206.0 SFFGCKD 3675 146.8 241.9 388.7 61.9 0.154 118.9 164.1 733.7 Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 6 33 Reference for Power Analysis
Reference J.
J. D. Alexander, Simulation Based Power
Estimation For Digital CMOS
Technologies, Master’s Thesis, Auburn
University, Dept. of ECE, December 2008.
University, Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 6 34 Low Power Scan FlipFlop
Reducing Shift Power
Scanin
DQ
FF1 DQ
FF2 DQ
FFN
Scanout Scan Enable
CLK
Copyright Agrawal, 2007
Copyright Multiphase
clock
generator
ELEC6270 Spring 11, Lecture 6 35 BuiltIn SelfTest (BIST)
Linear feedback shift register (LFSR)
Pseudorandom patterns BIST
Controller Circuit under test (CUT)
Circuit responses
Multiple input signature register (MISR) Clock C. E. Stroud, A Designer’s Guide to BuiltIn SelfTest, Boston: Springer,
2002.
Copyright Agrawal, 2007
Copyright ELEC6270 Spring 11, Lecture 6 36 Test Scheduling Example
R1 R2 M1 M2 R3 R4
A datapath Copyright Agrawal, 2007
Copyright ELEC6270 Spring 11, Lecture 6 37 BIST Configuration 1: Test Time M1 MISR1 LFSR2 M2 Test power LFSR1 T2: test for M2 T1: test for M1 MISR2
Test time Copyright Agrawal, 2007
Copyright ELEC6270 Spring 11, Lecture 6 38 BIST Configuration 2: Test Power M1 MISR1 Copyright Agrawal, 2007
Copyright LFSR2 M2 Test power R1 T1: test for M1 MISR2 ELEC6270 Spring 11, Lecture 6 T2: test for M2 Test time 39 Testing of MCM and SOC Test
Test resources: Typically registers and
multiplexers that can be reconfigured as test
pattern generators (e.g., LFSR) or as output
response analyzers (e.g., MISR).
response Test resources (R1, . . .) and tests (T1, . . .)
Test
are identified for the system to be tested.
are Each test is characterized for test time,
Each
power dissipation and resources it requires.
power
Copyright Agrawal, 2007
Copyright ELEC6270 Spring 11, Lecture 6 40 Resource Allocation Graph
(A Bipartite Graph)
T1 R1 R2 Copyright Agrawal, 2007
Copyright T2 R3 T3 R4 T4 R5 T5 R6 ELEC6270 Spring 11, Lecture 6 R7 T6 R8 R9 41 Definition: Bipartite Graph
Definition: A bipartite graph (or bigraph) iis a graph whose vertices
bipartite
bigraph s
can be divided into two disjoint sets U and V such that every
edge connects a vertex in U to one in V; that is, U and V are
that
independent sets.
Equivalently, a bipartite graph is a graph that does not
Equivalently,
contain any oddlength cycles.
contain
A bipartite graph has no clique of size 3 or larger.
A bipartite graph can be colored with two colors (chromatic
bipartite
number = 2).
number Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 6 42 Test Compatibility Graph (TCG)
T1
(2, 100)
T6
(1, 100) T2
(1,10) T5
(2, 10) T3
(1, 10) Power Pmax = 4
Copyright Agrawal, 2007
Copyright Test time T4
(1, 5) ELEC6270 Spring 11, Lecture 6 Tests that form a
clique can be
performed concurrently.
43 Definition: Clique
Definition: A clique is an undirected graph in which every vertex is
clique
connected to every other vertex .
connected
A clique is a complete graph.
the maximum clique problem, iis to find the largest
s
the maximum
clique in a graph.
clique
Finding whether there is a clique of a given size in a
Finding
graph (the clique problem) is NPcomplete.
graph
C. Bron and J. Kerbosch (1973): “Algorithm 457: Finding
C.
All Cliques of an Undirected Graph.,” Communications of
the ACM, vol. 16, no. 9. ACM Press: New York.
the Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 6 44 A Similar Definition: SCC
Similar A directed graph is called strongly connected if there is a
directed
strongly
path from each vertex in the graph to every other vertex.
path
The strongly connected components (SCC) of a directed
The strongly
of
graph are its maximal strongly connected subgraphs. If each
strongly connected component is contracted to a single
vertex, the resulting graph is a directed acyclic graph (DAG).
vertex,
T. H. Cormen, C. E. Leiserson, R. L. Rivest, and C. Stein. Introduction to
T.
Algorithms, Second Edition, MIT Press and McGrawHill, 2001, ISBN 0Algorithms
262032937.
Finding SCCs, O(V+E) Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 6 45 Find All Cliques in TCG
Find
CLIQUE NO. i TEST NODES TEST LENGTH, Li POWER, Pi 1 T1, T3, T5 100 5 2 T1, T3, T4 100 4 3 T1, T6 100 3 4 T1, T5 100 4 5 T1, T4 100 3 6 T1. T3 100 3 7 T2, T6 100 2 8 T2, T5 10 3 9 T3, T5 10 3 10 T3, T4 10 2 11 T1 100 2 12 T2 10 1 13 T3 10 1 14 T4 5 1 15 T5 10 2 16 T6 ELEC6270 Spring 11, Lecture 6100 1 Copyright Agrawal, 2007 46 Integer Linear Program (ILP)
Integer For each clique (test session) i, define: Integer
Integer variable, xi = 1, test session selected,
or xi = 0, test session not selected.
or Constants, Li = test length, Pi = power. Constraints to cover all tests: T1 is covered if x1+x2+x3+x4+x5+x6+x11 ≥ 1 Similar constraint for each test, Tk Constraints
Copyright Agrawal, 2007 for power: Pi × xi ≤ Pmax
ELEC6270 Spring 11, Lecture 6 47 ILP Objective and Solution
ILP Objective function: Minimize
Σ Li × xi
all cliques
all Solution: x3 = x8 = x10 = 1, all other xi’s are 0 Test session 3 includes T1 and T6
Test session 8 includes T2 and T5
Test session 10 includes T3 and T4 Test length = L3 + L8 + L10 = 120 Peak power = max {P3, P8, P10} = 3 (Pmax = 4)
Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 6 48 A System Example: ASIC Z*
RAM 2
Time=61
Power=241 ROM 1
Time=102
Power=279 RAM 3
Time=38
Power=213 ROM 2
Time=102
Power=279 Random logic 1, time=134, power=295
Random logic 2, time=160, power=352
RAM 4
Time=23
Power=96 RAM 1
Time=69
Power=282 Reg. file
Time = 10
Power=95 * Y. Zorian, “A Distributed Control Scheme for Complex VLSI Devices,”
Proc. VLSI Test Symp., April 1993, pp. 49.
Copyright Agrawal, 2007
Copyright ELEC6270 Spring 11, Lecture 6 49 ASIC Z Test ScheduleHeuristic Solution
1200 Reg. file
Power limit = 900 Power 900
600 RAM 3 RAM 2
Random logic 1 ROM 1 300
RAM 4
0 Random logic 2 RAM 1 ROM 2 200
300
400
Test time
331
R. M. Chou, K. K. Saluja and V. D. Agrawal, “Scheduling Tests for VLSI
Systems under Power Constraints,” IEEE Trans. VLSI Systems, vol. 5,
no. 2, pp. 175185, June 1997.
Copyright Agrawal, 2007
Copyright 100 ELEC6270 Spring 11, Lecture 6 50 ASIC Z: Better Solution
ASIC Obtainable from ILP: {RL1, RL2, RAM2}
Test length =160
{RAM1, ROM1, ROM2} Test length = 102
{RAM3, RAM4, RF}
Test length = 38
Total test length = 300
See, E. Larsson and C. P. Ravikumar, “PowerAware
See,
SystemLevel Test Planning,” Chapter 6, Section 6.4.1 in
PowerAware Testing and Test Strategies for Low Power
Devices, P. Girard, N. Nicolici and X. Wen (Eds.),
Devices P.
Springer, 2010.
Springer, Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 6 51 References N. Nicolici and B. M. AlHashimi, PowerConstrained Testing of
N.
VLSI Circuits, Boston: Springer, 2003.
VLSI E. Larsson, Introduction to Advanced SystemonChip Test Design
E.
and Optimization, Springer 2005.
and P. Girard, X. Wen and N. A. Touba, “LowPower Testing,” in System
P.
System
on Chip Test Architectures, L.T. Wang, C. E. Stroud and N. A.
on
L.T.
Touba, editors, MorganKaufman, 2008.
Touba, N. Nicolici and P. Girard, Guest Editors, “Special Issue on Low
N.
Power Test,” J. Electronic Testing: Theory and Applications, vol. 24,
no. 4, pp. 325–420, Aug. 2008.
no. P. Girard, N. Nicolici and X. Wen, PowerAware Testing and Test
P.
Strategies for Low Power Devices, Springer, 2010.
Strategies Copyright Agrawal, 2007
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