Lu_ELEC6970 - Minimizing Leakage Power in Dual-Threshold...

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Minimizing Leakage Power in Dual-Threshold CMOS Circuits Using Integer Linear Programming Yuanlin Lu and Vishwani D. Agrawal Auburn University, Department of ECE, Auburn, AL 36849 , ABSTRACT This paper presents a novel technique, which uses integer linear programming (ILP) to significantly reduce the leakage power without sacrificing circuit performance. For each gate in the design library low and high threshold versions are characterized for leakage in various input states using Spice simulation. An ILP model first finds the shortest critical path delay corresponding to all low- threshold gates. A second ILP model then minimizes the total leakage power by optimally placing high-threshold devices for a user-specified critical path delay. The constraint set sizes for both ILP models are linear in the circuit size. Experimental results show a 96% reduction of leakage power with no delay increase for the benchmark circuit C7522 implemented in the 70nm BPTM CMOS technology. Some other ISCAS’85 benchmarks had lower power savings, but when a 25% increase in the critical path delay was allowed all had at least 90% leakage reduction. Using an example, we outline a possible extension of the dual-threshold method to simultaneously minimize the leakage power and the dynamic glitch power, which is under investigation. 1. INTRODUCTION In the past, the dynamic power has dominated total power dissipation of a CMOS device. Since dynamic power is proportional to the square of the power supply voltage, lowering the voltage reduces the power dissipation. However, to maintain or increase the performance of a circuit, its threshold voltage should be decreased by the same factor, which increases the subthreshold (leakage) current of transistors exponentially [1]. Therefore, with the trend of CMOS technology scaling, leakage power is becoming a dominant contributor to the total power consumption. To reduce leakage power, a large number of techniques have been proposed, including transistor sizing [3-4], multi- V th [13- 15], dual- V th [3-6,12], optimal standby input vector selection [8-9], stacking transistors [11], etc. Dual- V th assignment is an efficient technique to decrease leakage power. To maintain the circuit performance, transistors in the gates on the critical path and a very small number of gates on non-critical paths should have low V th assignment, while all the other gates can be reassigned high V th . This leads to significant leakage reduction. Wei et al . [5] describe an algorithm to find an optimal assignment of V th that makes the number of high V th gates as large as possible. However, in reality, the two threshold voltages in a process are predetermined and the designer does not have the choice of arbitrary V th . Therefore, the algorithm is impractical. References [3-6, 12] propose various algorithms for
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This note was uploaded on 09/17/2011 for the course ELEC 6970 taught by Professor Staff during the Spring '08 term at Auburn University.

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Lu_ELEC6970 - Minimizing Leakage Power in Dual-Threshold...

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