NitinYogi_Logic_Redesign

# NitinYogi_Logic_Redesign - ELEC 6970 LOW POWER DESIGN FINAL...

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ELEC 6970 LOW POWER DESIGN FINAL PROJECT REPORT REDESIGN OF MULTIPLIER CELL LOGIC FOR LOW POWER By Nitin Yogi

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Introduction: In the design flow of digital circuits and systems, the process of logic synthesis and optimization plays an important role. It is mainly concerned with converting a behavioral level circuit to a gate level netlist trying to optimize one or more objectives of area, delay, power and testability. Logic synthesis for area and delay has been widely used in CAD tools in the industry. Low power and testability have yet to find a place in the commercial tools. Logic synthesis and optimization for Low power: The process of logic synthesis and optimization for low power can be divided into two techniques: 1) Technology Independent Optimization 2) Post Mapping Structural Optimization 1) Technology Independent Optimization: This technique mainly involves optimizations at the Boolean function level using kernels, cube extraction and iterative extraction and re-substitution of sub- expressions. 2) Post Mapping Structural Optimization: This technique can be further divided into two: a. Redundancy Insertion b. Logic Transformations Project objectives: In this project we design a hierarchical 32 x 32 bit multiplier using a 1 bit multiplier cell. The logic in the multiplier cell is to be redesigned to minimize power consumption. My work has mainly concentrated on the second method of post mapping structural optimization. For this an un-optimized gate level netlist as shown in Fig 1, is taken as the input to perform logic optimization for low power. Logic optimization of multiplier cell: Various techniques tried and used for logic optimization are as follows: 1) Logic transformations 2) Redundancy insertion 1) Logic transformations: Some of the goals for logic transformations were: a) Reduce number of transitions and glitches in the circuit b) Reuse or transform logic to reduce area and hence power consumption
Fig 1: Unoptimized multiplier cell netlist a) Reduce number of transitions and glitches in the circuit One of the ways of reducing the number of transitions in the circuit is, inverters if present should not be placed on signals with high activity. If the inverters are at the input of the circuit (assuming high signal activity at the inputs), then it is possible to redesign the logic to move or even eliminate some of the inverters. To illustrate this point let us consider a two input EX-OR gate. The logic function of an EX-OR gate is:

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## This note was uploaded on 09/17/2011 for the course ELEC 6970 taught by Professor Staff during the Spring '08 term at Auburn University.

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NitinYogi_Logic_Redesign - ELEC 6970 LOW POWER DESIGN FINAL...

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