Unformatted text preview: Logic Redesign for Low Power
ELEC 6970 Project Presentation
By Nitin Yogi
Nov. 29, 2005 ELEC6970-001 Class Presentation 1 Outline Low Power Logic Synthesis Low Power Optimization Techniques Redundancy Insertion Logic Transformation Multiplier Cell Optimization Experimental Results Summary and Conclusion What I learnt !
ELEC6970-001 Class Presentation 2 Nov. 29, 2005 Low Power Logic Synthesis Sources of Power Dynamic power Signal transitions Logic activity Glitches Short-circuit Leakage Static Power Area Method : Area optimized logic synthesis Method : Optimized transistor level design for gates Method : Low Power Logic Synthesis
ELEC6970-001 Class Presentation 3 Power Transistor Leakage and Short-circuit current Power Signal Activity of Circuit Nov. 29, 2005 Low Power Optimization techniques Technology Independent Optimization Algebraic Logic Restructuring
Kernel and Cube Extraction Iterative extraction and re-substitution of sub-expressions Post Mapping Structural Optimization Redundancy Insertion Logic Transformations Nov. 29, 2005 ELEC6970-001 Class Presentation 4 Post-mapping Structural Optimization Redundancy Insertion Redundancy is inserted into the circuit to minimize a cost function. 3 elements required in the process Suitable circuit location for redundancy insertion Candidate type of redundancy Cost function Identifying candidates for redundancy insertion at a suitable circuit location for minimum cost function. Applying logic transformation to insert redundancy Reducing the circuit by removing other generated redundancies by logic transformation.
ELEC6970-001 Class Presentation 5 3 steps involved Nov. 29, 2005 Post-mapping Structural Optimization Finding Circuit Locations for Redundancy Insertion Identify Source and Target locations using don't care implications
Possible target location x x A B x x x 0 0 Source location Y C D
Nov. 29, 2005 ELEC6970-001 Class Presentation 6 Post-mapping Structural Optimization Candidate Redundancy insertions Redundancy insertions to input of gates
x x 0 `0' implication don't care 1 `1' implication don't care Used to reduce signal activity at the output of a gate using another signal.
ELEC6970-001 Class Presentation 7 Nov. 29, 2005 Gate Insertion: Post-mapping Structural Optimization Nov. 29, 2005 ELEC6970-001 Class Presentation 8 Post-mapping Structural Optimization Circuit Reduction to eliminate unwanted redundancies Redundancy identification methods: ATPG based
Use of exhaustive ATPG to find redundant faults Redundant faults signify redundant logic Fault independent Controllability and Observability analysis
ELEC6970-001 Class Presentation 9 Nov. 29, 2005 Post-mapping Structural Optimization
Logic Transformations Permissible function: If all the network primary output functions do not change after the function realized at a signal line Li is replaced by a function f , then the function f is called a permissible function for the signal line Li . Gate Substitution Replace a target signal line with the candidate signal line having the same function. Replace a target signal line with the inverted candidate signal line having the same function.
ELEC6970-001 Class Presentation 10 Inverter Insertion Nov. 29, 2005 Post-mapping Structural Optimization Logic Transformations Eliminate inverters on signals with high activity Discourage the implementation of EX-OR gates EX-OR gate example: Y = AB + AB = (AB) + (AB) = (A + B) + AB Nov. 29, 2005 ELEC6970-001 Class Presentation 11 Multiplier Cell
B3 0 B2 0 B1 0 B0 0 A0 0 Y0 0 A1 Y1 A2 0 Y2 A3 0 Y7 Y6 Y5 Y4 Y3 B Sum input A Carry out Full adder Carry in Sum output Array Cell Full Adder Nov. 29, 2005 ELEC6970-001 Class Presentation 12 Multiplier Cell
EX-OR EX-OR Nov. 29, 2005 ELEC6970-001 Class Presentation 13 Multiplier Cell
EX-OR EX-OR Nov. 29, 2005 ELEC6970-001 Class Presentation 14 Multiplier Cell
Modified - 2 Nov. 29, 2005 ELEC6970-001 Class Presentation 15 Multiplier Cell Leonardo (delay optimized) Nov. 29, 2005 ELEC6970-001 Class Presentation 16 Multiplier Cell
Leonardo (area optimized) Nov. 29, 2005 ELEC6970-001 Class Presentation 17 Experimental Results
Multiplier Cell Design and simulation details Design Entry tool: Design Architect Simulation tool : Eldo (timing and power analysis) Technology library: tsmc 0.18um (VDD = 1.8V) Inputs: frequencies in multiples of 2 Output transitions generated: Input Vectors: Sum Out (Sout) : 25 Carry Out (Cout) : 12
ELEC6970-001 Class Presentation 18 Nov. 29, 2005 Multiplier Cell Results
Unopt. Static Power Dyn. Power Tdelay
(A/B=>Sout) Opt. Leo_Area Leo_Delay 367.04 pW 201.93 pW 168.94 pW 194.28 pW 27.08 uW Avg. Peak Avg. Peak 276.13 ps 328.45 ps 226.08 ps 237.07 ps 17.39 uW 287.77 ps 345.74 ps 173.77 ps 177.02 ps 20.83 uW 225.85 ps 257.23 ps 80.59 ps 108.62 ps 21.28 uW 189.16 ps 255.17 ps 90.16 ps 96.60 ps
Nov. 29, 2005 ELEC6970-001 Class Presentation Summary and Conclusion Post Mapped Structural Optimization techniques for Low Power prove to be effective. Percentage reduction in power consumption of optimized Multiplier Cell as compared to: Unoptimized cell: ~35.7% Leonardo generated: ~15% Percentage increase in critical path delay of optimized Multiplier Cell as compared to: Unoptimized cell: ~35.7% Leonardo generated: ~50% Effective cost functions to include delay constraints will enhance the quality of the circuits. Effective algorithms for structural optimization. 32 x 32 bit Multiplier power optimization.
ELEC6970-001 Class Presentation 20 Nov. 29, 2005 What I learnt ! Low Power Logic Synthesis Logic synthesis Logic optimization Redundancy insertion, identification and elimination Use of EDA tools for timing and power analysis Start your projects early! (wish I would have) Large patience required with EDA tools!
ELEC6970-001 Class Presentation 21 Nov. 29, 2005 References
1. 2. 3. 4. 5. 6. S. Devadas, S. Malik, "A Survey of Optimization Techniques Targeting Low Power VLSI Circuits," Annual ACM IEEE Design Automation Conference, Proceedings of the 32nd ACM/IEEE conference on Design automation, San Francisco, California, United States, pp. 242 247, 1995 Pradhan D.K., Chatterjee M., Swarna M.V., Kunz W, "Gate-level synthesis for lowpower using new transformations," Low Power Electronics and Design, 1996, International Symposium on, pp 297-300, Aug 1996 Wang Q., Vrudhula S.B.K., "Multi-level logic optimization for low power using local logic transformations," Computer-Aided Design, 1996. ICCAD-96., 1996 IEEE/ACM International Conference on 10-14 Nov. 1996 Page(s):270 277 Shih-Chieh Chang, Marek-Sadowska M, "Perturb And Simplify: Multi-level Boolean Network Optimizer," Computer-Aided Design, 1994., IEEE/ACM International Conference on November 6-10, 1994 Page(s):2 - 5 R. V. Menon, S. Chennupati, N. K. Samala, D. Radhakrishnan and B. Izadi, "Power Optimized Combinational Logic Design," Proceedings of the International Conference on Embedded Systems and Applications, pp. 223 - 227, June 2003. W. Kunz, "Multi-level Logic Optimization By Implication Analysis," ComputerAided Design, 1994., IEEE/ACM International Conference on November 6-10, 1994 Page(s):6 - 13
ELEC6970-001 Class Presentation 22 Nov. 29, 2005 References
1. 2. 3. 4. 5. Roy K., Prasad S.C., "Circuit activity based logic synthesis for low power reliable operations," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on Volume 1, Issue 4, Dec. 1993, pp 503 513 Ki-Wook Kim, Ting Ting Hwang, Liu C.L., Sung-Mo Kang, "Logic transformation for low power synthesis," Design, Automation and Test in Europe Conference and Exhibition 1999. Proceedings, pp158 162, March 1999 Brzozowski I., Kos A., "Minimisation of power consumption in digital integrated circuits by reduction of switching activity," EUROMICRO Conference, 1999. Proceedings. 25th Volume 1, 8-10 Sept. 1999 Page(s):376 - 380 vol.1 M. A. Iyer and M. Abramovici, "Low-Cost Redundancy Identification for Combinational Circuits," in Proc. 7th International Conf. on VLSI design, pp. 315317, January 1994. V.D. Agrawal; M.L. Bushnell, Qing Lin, "Redundancy identification using transitive closure," Test Symposium, 1996., Proceedings of the Fifth Asian 20-22 Nov. 1996 Page(s):4 9 Abramovici M., Iyer M.A., "One-Pass Redundancy Identification and Removal," Test Conference, 1992. Proceedings., International Sept. 20-24 1992 Page(s):807
ELEC6970-001 Class Presentation 23 Nov. 29, 2005 Thank You!
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