paper_dixit - Abstract Two new test generation algorithms...

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Unformatted text preview: Abstract Two new test generation algorithms for combinational and sequential circuits have been proposed. Test vectors are generated using characteristic faults and spectral information embedded in a circuit under test (CUT) in the form of Hadamard coefficients for the circuits. The Hadamard coefficients are extracted using input and output correlation for combinational circuits and using a test vectors targeted for a small set of faults in the circuits for sequential circuits often known as characteristic faults. 1. Introduction Due to the advancement of the technology in terms of device density and clock speed, testing of the devices have posed a threat to design engineers. Market drive and feature requirements supported by devices have led designers to use complex designs that are hard to test. Researchers in the past have come up with different algorithms and innovative ways to test devices but the increment in device complexity has rendered those methods insufficient if not useless. Test equipments to test a device are falling short on keeping pace with the increasing operating speed of the device preventing “at speed” testing [2]. At-speed testing is crucial for reduction of test time which is the reason Built-in-self- test (BIST) solutions have become part of designs these days. BIST solutions comprise of test pattern generator (TPG) that generates the vector sequence to be applied to the circuit under test (CUT), response compactor that compacts the responses obtained from the CUT into a signature and an output response analyzer (ORA) that compares the signature to the signature of the fault free circuit stored in the device. In most of the BIST schemes, TPGs use linear feedback shift register (LFSR) to produce pseudo-random patterns. They have a simple structure and can also be used as output response analyzers, thereby serving dual purpose [1]. The quality of the LFSR-generated test set depends on the CUT [3] . Random technique results in large test sets [2] and is useful for circuits without random-pattern -resistant faults [3]. Weighted random patterns have been found to yield better fault coverage in circuits that contain random- pattern-resistant faults [4][5]. The basic idea for weighted pseudo random test pattern generation method is to bias the probability at each input based on the information gathered on the circuit [6]. Weighting the pseudo-random patterns [7-8] is done using counter-based schemes [9-10] or performing bit-fixing (pattern mapping)[11]. However, the difficulty arises when no one set of weights may be suitable for all faults [12], and some structures in logic circuits are resistant even to weighted random testing [14]. Many hardware pattern generators often round-off optimal weights producing patterns that are sub-optimal for certain circuits [6]....
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This note was uploaded on 09/17/2011 for the course ELEC 6970 taught by Professor Staff during the Spring '08 term at Auburn University.

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paper_dixit - Abstract Two new test generation algorithms...

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