Ramkumar_DualVoltage

Ramkumar_DualVoltage - ELEC6970 LowPowerDesignProject...

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ELEC 6970  Low Power Design Project Dual-Voltage Supply for Power Reduction Muthubalaji Ramkumar
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Objective To use a Dual-Voltage Supply in order to reduce the power consumption of the 32 x 32  bit   integer   array   multiplier   circuit   designed   in   0.18 μ   CMOS   technology   without  compromising the critical delay. Verification of logical correctness The array multiplier circuit was coded in VHDL  It was compiled and simulated using ModelSim SE PLUS 5.8c  The logical correctness of the multiplier was   verified by forcing several input  vectors using the ModelSim SE PLUS 5.8c simulator Synthesis of the design Leonardo   Spectrum,   a   versatile   and   interactive   logic   synthesis,   optimization,   and  analysis tool was used for synthesis of the circuit described in VHDL. The inputs to the  synthesis process are a VHDL description, attributes for the design and a technology  library which produces an optimized gate level netlist. The VHDL code for the design  was synthesized using Leonardo Spectrum which created the optimized netlist which  was ready to be imported in to the power estimation tool. Power Estimation and Critical Delay Design   Architect   –   IC  contains   a   schematic   editor   and   was   used   for   creating   the  technology   specific   schematic   by   importing   the   netlist   created   in   verilog   using   the  Leonardo synthesis tool. Eldo, the spice simulator in Design Architect was used for 
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performing a transient analysis by forcing input vectors in order to estimate the power  and critical delay. The standard Vdd for 0.18
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Ramkumar_DualVoltage - ELEC6970 LowPowerDesignProject...

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