Ramkumar_DualVoltage

Ramkumar_DualVoltage - Dual­Voltage Supply for Power...

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: Dual­Voltage Supply for Power Reduction ELEC 6970 – Low Power Design Project Presentation by Muthubalaji Ramkumar December 1, 2005 December ELEC 6970 - Project Presentation 1 Problem Statement To Use a dual­supply voltage in order to reduce the power consumption of the 32 x 32 bit integer array multiplier circuit without compromising the overall delay December 1, 2005 December ELEC 6970 - Project Presentation 2 Power and Delay Power → VDD2 Delay → KVDD ─────── (VDD – Vt)α December 1, 2005 December ELEC 6970 - Project Presentation 3 Approach Low Voltage Assignment to as many cells as possible The interconnections in this multiplier circuit makes it difficult Therefore assign Low Voltage Supply to as many gates as possible December 1, 2005 December ELEC 6970 - Project Presentation 4 Things to watch Reducing the Voltage Supply will increase the delay of a gate Therefore assign Low­Voltage Supply only to the gates which do not have any influence on the Critical Path Delay directly or indirectly Low voltage gate should have adequate voltage swing in order to drive a High Voltage gate its feeding in to. December 1, 2005 December ELEC 6970 - Project Presentation 5 4 x 4 Multiplier B3 0 B2 0 B1 0 B0 0 B Sum input A0 0 A Y0 0 A1 Y1 A2 Carry out 0 Y2 Full adder Carry in A3 0 Y7 Y6 Y5 Y4 Array December 1, 2005 December Sum output Y3 ELEC 6970 - Project Presentation Cell 6 Multiplier Cell December 1, 2005 December ELEC 6970 - Project Presentation 7 Low­Voltage Supply Assignment Output Cells along the edge N­1 G4 First Row 3(N­1) G1,G2,G3 Second Row to Last Row N(N­1) G1 Left Column 2(N­1) G2,G3 December 1, 2005 December ELEC 6970 - Project Presentation 8 Total Number of gates = 6N2 Number of gates with Low Voltage assignment = (N­1)(N+6) Percentage of the circuit with Reduced VDD = December 1, 2005 December (N­1)(N+6) / 6N2 ELEC 6970 - Project Presentation 9 Percentage of the Circuit with Reduced Voltage Supply P r e ta eo G te u d r L wV lta eS p ly ec n g f a s n e o o g up 3 4 3 2 3 0 2 8 2 6 2 4 2 2 2 0 1 8 1 6 0 December 1, 2005 December 2 0 4 0 6 0 8 0 N- N o b o f its 10 0 ELEC 6970 - Project Presentation 10 2 10 4 10 Experimental Results for a Cell Voltage Pdyn Pstatic Delay (Volts) (Microwatts) (Picowatts) 1.8 9.1 246 251 p 1.5 5.27 171 358 p 1.2 2.87 112 537 p 0.9 0.79 67 1.14 n December 1, 2005 December ELEC 6970 - Project Presentation (Sec) 11 Experimental Results for a 4 x 4 Multiplier Voltage Pdyn Pstatic Delay (Volts) (Microwatts) (Nanowatts) 1.8 213 1.6 1.57 n 1.5 132.1 1.13 1.76 n 1.2 75.8 0.75 1.97 n 0.9 36.4 0.46 2.2 n December 1, 2005 December ELEC 6970 - Project Presentation (Sec) 12 A Single Inverter Voltage Pdyn Pstatic Delay (Volts) (Microwatts) (Picowatts) 1.8 1.88 10 82 p 1.5 0.588 7 91 p 1.2 0.114 4.6 108 p 0.9 0.047 2.8 236 p December 1, 2005 December ELEC 6970 - Project Presentation (Sec) 13 4 x 4 bit array Multiplier N=4 Total Number of Gates = 6N2 = 6(16) = 96 Number of Gates with Low VDD = (N­1)(N+6) = (3)(10) = 30 = 31.25 % Number of Gates with Normal VDD = 96 – 30 = 66 = 68.75% December 1, 2005 December ELEC 6970 - Project Presentation 14 Power Estimation Using Dual­Voltages, 1.8V & 1.5V Power Consumption = (0.3125)(132.1uW) + (0.6875)(213uW) = 187.73 uW 12% Power Reduction December 1, 2005 December ELEC 6970 - Project Presentation 15 Power Estimation Using Dual­Voltages, 1.8V & 1.2V Power Consumption = (0.3125)(75.8uW) + (0.6875)(213uW) = 170.125 uW 20.13 % Power Reduction December 1, 2005 December ELEC 6970 - Project Presentation 16 32 x 32 bit array Multiplier N=32 Total Number of Gates = 6N2 = 6(1024) = 6144 Number of Gates with Low VDD = (N­1)(N+6) = (31)(38) = 1178 = 19.2 % Number of Gates with Normal VDD = 6144 – 1178 = 4966 = 80.8% December 1, 2005 December ELEC 6970 - Project Presentation 17 Power Estimation Using Dual­Voltages, 1.8V & 1.5V Power Consumption = (0.192)(8.45mW) + (0.808)(13.63mW) = 12.64 mW 7.3% Power Reduction December 1, 2005 December ELEC 6970 - Project Presentation 18 Power Estimation Using Dual­Voltages, 1.8V & 1.2V Power Consumption = (0.192)(4.85mW) + (0.808)(13.63mW) = 11.9 mW 12.4% Power Reduction December 1, 2005 December ELEC 6970 - Project Presentation 19 Conclusion Pros… Reduction in power Delay is not compromised No change in Area Dual­power supply is easy to generate using potential dividers Cons… The percentage of the circuit that can be fed with Low Voltage supply is less Requires careful assignment of Low Voltage Supply December 1, 2005 December ELEC 6970 - Project Presentation 20 Comments Learnt VHDL basics Introduction to very useful EDA tools Get a feel of VLSI Design Appreciation of Low Power Design Time Consuming but worth it December 1, 2005 December ELEC 6970 - Project Presentation 21 ...
View Full Document

This note was uploaded on 09/17/2011 for the course ELEC 6970 taught by Professor Staff during the Spring '08 term at Auburn University.

Ask a homework question - tutors are online