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Unformatted text preview: Leakage Power
Reduction Techniques
Reduction
Yuanlin Lu
ECE Dept. Auburn University
ELEC 6970 Outline
Transistor Leakage Mechanisms
Leakage Reduction techniques
 Mutli, dual, Variable Vth
Mutli,
 Dual Power Supply
Dual
 Transistor Sizing
Transistor
 Transistor Stacking
Transistor
 Optimal Input Vector Selection
Optimal Proposed Technique
 Using ILP to Minimize leakage
Using
 Extend ILP to Minimize leakage and Glitch Power together 09/17/11 ELEC 6970 2 Transistor Leakage Mechanisms I2, I5, I6 and are offstate leakage
I2,
mechanisms;
I1 and I3 occur in both ON and OFF
states;
states;
I4 can occur in the off state, but more
I4
typically occurs during the transistor
bias states in transition.
bias
09/17/11 ELEC 6970 I1  the reversebias pn junction
I1
leakage;
leakage;
I2  the subthreshold leakage; weak
I2 the
weak
inversion conduction current between
source and drain in an MOS transistor
occurs when gate voltage is below Vth.
occurs
I3  the oxide tunneling current; due to
I3
the low oxide thickness and the high
electric field;
electric
I4  the gate current due to hotcarrier
I4
injection;
I5  the GIDL (GateInduced Drain
I5
Leakage); due to high field effect in the
Leakage) due
drain junction;
I6  the channel punchthrough current;
due to the proximity of the depletion
regions of the drain and the source.
regions 3 Subthreshold Leakage current
I sub = u0Cox Weff
Leff Vgs − Vth
VT e exp nV
T 2 1 .8 1 − exp − Vds
⋅ V T u0 is the zero bias electron mobility, n is the subthreshold slope coefficient.
u0
is To decrease Subthreshold current
To
Cox = εox/Tox Determined by foundry
Vgs & Vds Vdd dual power supply
dual
Vth dualVth, MultiVth, Variable Vth
dualVth,
W or L gate sizing
gate
Temperature ( VT = KT/q)
Temperature
KT/q)
09/17/11 ELEC 6970 4 Outline
Transistor Leakage Mechanisms
Leakage Reduction techniques
Leakage
 Mutli, dual, Variable Vth
Mutli,
 Dual Power Supply
Dual
 Transistor Sizing
Transistor
 Transistor Stacking
Transistor
 Optimal Input Vector Selection
Optimal Proposed Technique
Proposed
 Using ILP to Minimize leakage
Using
 Extend ILP to Minimize leakage and Glitch Power together
Extend 09/17/11 ELEC 6970 5 Leakage & Delay
Leakage
Increasing Vth can decrease Isub exponentially
sub exponentially
Increasing
But, gate delay increase at the same time
But,
T pd ∝ CVdd (Vdd − Vth ) α where α models short channel effects (1.3)
models
When using Vth changing techniques, must
When
consider the tradeoff between leakage
reduction and performance reduction
reduction
09/17/11 ELEC 6970 6 MTCMOS (MultiThreshold CMOS) 09/17/11 ELEC 6970 7 MTCMOS (cont.)
Advantage
 Circuit can be modified
Circuit
easily
easily
Disadvantages
 Affect delay, area
 Can only reduce leakage
Can
power in standby mode
power
 Not suitable for sequential
Not
circuit
circuit
09/17/11 ELEC 6970 8 VTMOS (Variable Threshold
VTMOS
CMOS)
CMOS) ( Vth = Vth 0 − ηVds + r Vsb + 2Φ F − 2Φ F
Vth0
r
2ФF
η  zerosubstratebias value for Vth
 body effect parameter
 surface potential parameter
 Draininduced barrier lowering (DIBL)
coefficient (0.020.1) Using body effect, change Vth
In active mode, a zero body bias
In standby mode, a deeper reverse body bias, Vth increase
Can only reduce leakage power in standby mode 09/17/11 ELEC 6970 9 ) VTMOS (cont.) 09/17/11 ELEC 6970 10
10 Dual Threshold CMOS
To maintain performance, all
To
gates on the critical path are
assigned low Vth
assigned
Part of the gates on the noncritical paths are assigned high
critical
Vth
Vth
Disadvantage: Circuit structure
Disadvantage:
sensitive
sensitive
Advantage: Can reduce leakage
Advantage:
power in both standby mode and
active mode !
active 09/17/11 ELEC 6970 11
11 Outline
Transistor Leakage Mechanisms
Leakage Reduction techniques
Leakage
 Mutli, dual, Variable Vth
Mutli,
 Dual Power Supply
Dual
 Transistor Sizing
Transistor
 Transistor Stacking
Transistor
 Optimal Input Vector Selection
Optimal Proposed Technique
Proposed
 Using ILP to Minimize leakage
Using
 Extend ILP to Minimize leakage and Glitch Power together 09/17/11 ELEC 6970 12
12 Dual Power Supply Voltages
I sub = u0Cox Vgs − Vth 1 − exp − Vds VT e exp nV ⋅ V Leff
T T Weff 2 1.8 Vdd Isub gate delay
gate
Assign Low Vdd to the gates on the noncritical path, to decrease leakage power
Assign High Vdd to the gates on the critical
Assign
path, to maintain performance
path, 09/17/11 ELEC 6970 13
13 Outline
Transistor Leakage Mechanisms
Leakage Reduction techniques
Leakage
 Mutli, dual, Variable Vth
Mutli,
 Dual Power Supply
Dual
 Transistor Sizing
Transistor
 Transistor Stacking
Transistor
 Optimal Input Vector Selection
Optimal Proposed Technique
Proposed
 Using ILP to Minimize leakage
Using
 Extend ILP to Minimize leakage and Glitch Power together 09/17/11 ELEC 6970 14
14 Transistor Stacking
Serious connected ‘off’ Transistors (Transistor Stacking)
Serious
can reduce leakage current greatly
can
I sub = u0Cox Vgs − Vth −V 2 ⋅ 1 − exp ds VT e1.8 exp nV V Leff
T T Weff ( Vth = Vth 0 − ηVds + r Vsb + 2Φ F − 2Φ F
Vdd Vdd
0 0 0 0 M GND 09/17/11 0
Vdd=Vds M1 0 M2 Vm Vdd=Vds1+ Vds2 GND ) When M1 and M2 are turned off, Vm
at the intermediate node is positive
due to small drain current.
due
Vgs1 < 0, reduce the subthreshold
Vgs1
current substantially.
current
Vbs1 < 0, increase Vth1 (larger body
Vbs1
effect) and thus reducing the
subthreshold leakage.
subthreshold
Vds1 decrease, increase Vth1
Vds2 decrease, increase Vth2 ELEC 6970 15
15 Outline
Transistor Leakage Mechanisms
Leakage Reduction techniques
Leakage
 Mutli, dual, Variable Vth
Mutli,
 Dual Power Supply
Dual
 Transistor Sizing
Transistor
 Transistor Stacking
Transistor
 Optimal Input Vector Selection
Optimal Proposed Technique
Proposed
 Using ILP to Minimize leakage
Using
 Extend ILP to Minimize leakage and Glitch Power together 09/17/11 ELEC 6970 16
16 Leakage Dependence
Leakage
on the Input Vector
on
Different Input vector, different leakage current.
V dd
P1 P2 N1 N2
GN D 09/17/11 00: p1 & p2 on, n1 & n2 off.
Ileak 00 = In1 + In2 = 2 * Ileak
00
01: n1 off. n2 is on and can be treated as shorted,
so leakage current of n1 is ignored.
so
p1 is on and p2 is off.
Ileak 01 = Ip2 = Ileak
p2
10: the same as the ‘01’
Ileak 10 = Ip1 = Ileak
11: n1 & n2 on. p1 & p2 off. Due to the stacking
effect,
Ileak 11 < Ileak
So, when the input vector is ‘00’, the NOR gate has
So,
the maximal leakage current. When the input
vector is ‘11’, the NOR gate has the minimum
leakage current.
leakage
ELEC 6970 17
17 Optimal Input Vectors Selection
There must be optimal primary input vectors which lead to
There
the minimum leakage power in the standby mode.
standby
For smaller ciruits
For
 Exhaustive Search
For larger circuits
For
 Random Search
 Genetic algorithm ( exploit historical information to
enetic
speculate on new search points with expected improved
performance to find a nearoptimal solution )
performance 09/17/11 ELEC 6970 18
18 Outline
Transistor Leakage Mechanisms
Leakage Reduction techniques
Leakage
 Mutli, dual, Variable Vth
Mutli,
 Dual Power Supply
Dual
 Transistor Sizing
Transistor
 Transistor Stacking
Transistor
 Optimal Input Vector Selection
Optimal Proposed Technique
Proposed
 Using ILP to Minimize leakage
Using
 Extend ILP to Minimize leakage and Glitch Power together 09/17/11 ELEC 6970 19
19 Dual Threshold CMOS
To maintain performance, all
To
gates on the critical path are
assigned low Vth
assigned
Part of the gates on the noncritical paths are assigned high
critical
Vth, to avoid the change from
noncritical path to critical path.
noncritical
Disadvantage: Circuit structure
Disadvantage:
sensitive
sensitive
Advantage: Can reduce leakage
Advantage:
power in both standby mode and
active mode !
active
09/17/11 ELEC 6970 20
20 Using ILP (Integer Linear
Using
Programming) to Reduce Leakage
Power
Power In dualthreshold CMOS process
Firstly, assign all gates low Vth
Use ILP model 1 to find the delay of the
Use
critical path (Tc)
critical
Use ILP model 2 to find the optimal Vth
Use
assignment as well as the leakage
reduction of all gates without increasing Tc
reduction
Further reduce leakage power by
Further
increasing Tc
increasing 09/17/11 ELEC 6970 21
21 ILP
Raja et al. [16] proposed a technique to
Raja et
[16]
reduce dynamic glitch power by a reduced
constraint set linear program.
We modify their formulation into an integer
linear program (ILP) to reduce leakage
power.
power.
ILP is a mixed ( integer value and
ILP
continuous values combined together)
linear programming
linear
09/17/11 ELEC 6970 22
22 ILP Variables
Each gate has two variables.
Each
Ti: the latest time at which the output of gate i
the
can produce an event after the occurrence of an
input event at primary inputs of the circuit.
Continuous value
Continuous
Xi: the assignment of low or high Vth to gate i;
the
Vth
Xii is an integer which can only be 0 or 1.
X
integer
1 gate i is assigned low Vth;
Vth;
0 gate i is assigned high Vth.
Vt
09/17/11 ELEC 6970 23
23 ILP  objective function
objective
Pleak = Vdd ∑ I leaki
i objective function
 minimize the sum of all gates leakage
currents, which is given by Min∑ ( X i ⋅ I Li + (1 − X i ) ⋅ I Hi )
i 09/17/11 ILi is the leakage current of gate i with low Vth;
Li
Vth
IHi is the leakage current of gate i with high Vth;
Vth
Each gate’s leakage current can be either ILi or IHi;
Li
Each
Using SPICE simulation results, we constructed a
Using
leakage current look up table, which is indexed by
the gate type and the input vector.
the
ELEC 6970 24
24 ILP  Constraints
Constraints
Constraints for each gate
Constraints
(1)
(1) Ti ≥ T j + X i ⋅ DLi + (1 − X i ) ⋅ DHi gate j ‘s output is gate i ‘s fan in
gate
(2) 0 ≤ Xi ≤1 Max delay constraints for primary outputs (PO)
Max
(3) Ti ≤ Tmax
Tmax can be spec. or the delay of the critical path
max can 09/17/11 ELEC 6970 25
25 ILP – Constraints 1
Constraints
0 1 2
3 Ti ≥ T j + X i ⋅ DLi + (1 − X i ) ⋅ DHi
assume all primary input (PI) signals on the left arrive at the
assume
same time.
For gate 2, constraints can be given by
For T2 ≥ T0 + X 2 ⋅ DL 2 + (1 − X 2 ) ⋅ DH 2 T2 ≥ 0 + X 2 ⋅ DL 2 + (1 − X 2 ) ⋅ DH 2
09/17/11 ELEC 6970 26
26 ILP – Constraints 1 (cont.)
Constraints
DHi is the delay of gate i with high Vth;
DLi is the delay of gate i with low Vth.
A second lookup table is constructed and
second
specifies the delay for given gate type and
fanout number.
fanout 09/17/11 ELEC 6970 27
27 ILP – Constraints 3
Constraints
Ti ≤ Tmax
Tmax can be spec. or the delay of the critical path (Tc).
can
To find Tc, we change constraints 2 to a equation, which
To
Tc we
means all gates are assigned low Vth.
means Xi =1 0 ≤ Xi ≤1 The maximum Tii given by AMPL CPLEX, is equal to Tc.
The
T
Tc.
If we replace Tmax with Tc, the real objection function
If
Tc the
becomes minimize leakage power without sacrificing any
performance.
performance.
09/17/11 ELEC 6970 28
28 ILP – Constraints 3 (cont.)
Constraints 09/17/11 ELEC 6970 1
0.9
0.8
Normalized Leakage Power If we gradually increase Tmax from the
If
smallest value Tc, more leakage power
can be reduced, because more gates
on the noncritical path can be assigned
high Vth.
high
But, the reduction trend becomes
But,
slower.
slower.
When Tmax = (130%) Tc, the reduction
When
is saturated, because almost all the
gates are assigned high Vth, and there
is no more optimization space.
is
The maximum leakage reduction can
The
be 98%. C432
0.7
C880
0.6 C1908 0.5
0.4
0.3
0.2
0.1
1 1.1 1.2 1.3 1.4 1.5 Normalized Critical Path D
elay Tradeoff between Leakage and
Performance
Performance 29
29 ResultsLeakage Reduction
Cir. Number
of gates Tc
(ns) Unoptimize
d
Ileak (μA) Optimized
Ileak (μA)
(T = T ) Leakage
Reduction
% Sun
OS 5.7
CPU secs. Optimized for
Ileak (μA)
max (T 09/17/11 ELEC 6970 c Leakage
Reduction
% Sun
OS 5.7
CPU secs. =1.25T ) 30
30 ResultsDynamic & Leakage
ResultsDynamic
Comparison
Comparison
I sub = u0Cox Vgs − Vth −V 2 ⋅ 1 − exp ds VT e1.8 exp nV V Leff
T T Weff VT (thermal voltage, kT/q) and Vth both depend on the
kT/q and Vth
temperature, so, leakage current also strongly depends
on the temperature.
on
Spice simulation shows that for a 2input NAND gate
Spice
 with low Vth, Isub @ 90ºC = 10 * Isub @ 27ºC
Vth
 with high Vth, Isub @ 90ºC = 20 * Isub @ 27ºC
Vth
To manifest the projected contribution of leakage to the
total power, we compare dynamic and leakage power @
90ºC.
90
09/17/11 ELEC 6970 31
31 ResultsDynamic & Leakage
ResultsDynamic
Comparison (cont.)
Comparison
Without considering glitches, the dynamic
Without
power is estimated by an event driven
simulator, and is given by
simulator,
0.5 ⋅ Cinv ⋅ Vdd ⋅ ∑ Ti FOi
2 Pdyn = Edyn
T = i 1000(1.2 ⋅T c ) We apply 1000 random test vectors at PIs
We
with the test period equal to (120%)Tc,
with
Tc,
and calculate the total transition No. in the
circuit.
09/17/11 ELEC 6970 32
32 ResultsDynamic & Leakage
ResultsDynamic
Comparison (cont. 2)
Comparison
Circuit Pdyn
(μW) Pleak1
(μW) P leak2 /
Pleak2
(μW) P
P 09/17/11 / dyn % ELEC 6970 33
33 Outline
Transistor Leakage Mechanisms
Leakage Reduction techniques
Leakage
 Mutli, dual, Variable Vth
Mutli,
 Dual Power Supply
Dual
 Transistor Sizing
Transistor
 Transistor Stacking
Transistor
 Optimal Input Vector Selection
Optimal Proposed Technique
Proposed
 Using ILP to Minimize leakage
Using
 Extend ILP to Minimize leakage and Glitch Power together 09/17/11 ELEC 6970 34
34 Extend ILP to Minimize leakage and
Extend
Glitch Power together
Glitch
1. 4 1.8 1. 44
1. 3. 0 2.1 3.0 1. 5 1.8
1.4
1.5 1. 5 1.5
1.5 1. 5 3.0 Fig 1. A circuit with potential glitches
Fig
1.4 1.5 0.1 1.4
1.4 3.0
1.5 1.5
1.5
3.0 Fig 2. Inserting buffers in the
circuit of Figure 1 to balance the path
delays to eliminate all glitches.
delays 09/17/11 Fig 3. Hazard filter effect of high Vth gates . • Three black gates are assigned high Vth.
• Their delays increase accordingly.
• Only two buffers are needed to eliminate
all glitches due to the increased gate delay
of high Vth gates.
• This hazard filter effect is another
advantage of dualVth reassignment. ELEC 6970 35
35 Extend ILP to Minimize leakage and
Extend
Glitch Power together (cont.)
Glitch
The inserted buffers for eliminating glitches
The
consume additional leakage power, so, we may
assign high Vth to them.
Vth
Most of the delay buffers are on noncritical
paths and can be assigned high Vth.
Vth
For a larger circuit, the power saving due to
hazard filtering would be significant while power
increase due to delay buffers will be small 09/17/11 ELEC 6970 36
36 Future Work
Using ILP to minimize leakage and
dynamic power simultaneously.
dynamic
Consider transistor sizing to reduce
dynamic switching power and leakage
power simultaneously.
power 09/17/11 ELEC 6970 37
37 Thank You All !
Thank ...
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