Test_6270_sol - ELEC 5270/ELEC 6270 Low-Power Design of...

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ELEC 5270/ELEC 6270 Low-Power Design of Electronic Circuits Class Test, March 30, 2011 Total 25 points Broun 102, 3:00-3:50PM Instructions: Please read all problems before writing your answers. Attempt all six problems. Be sure to revise your answers before turning them in. Please number your answer sheets, and on the first page identify the test as shown above, write your name and the total number of pages, and staple them before submitting. One point is reserved for neatness. Thank you. Problem 1 (5 points): State the requirement on the supply voltage such that the short- circuit power is completely eliminated. Then show that when the power supply voltage VDD is in the range Max{|Vtp|, Vtn} ≤ VDD ≤ |Vtp| + Vtn The gates will work as switching devices without consuming any short-circuit power. Here Vtp and Vtn are the threshold voltages of the pMOS and nMOS transistors, respectively. Answer: The requirement for zero short-circuit power is: VDD ≤ |Vtp| + Vtn (1) For an nMOS transistor to turn on, i.e., get into the saturation mode, the controlling gate voltage must be at least Vtn. That is: Vtn ≤ VDD (2) Similarly, for the pMOS transistors to fully turn on the logic 0 level should be lower than VDD at least by the amount |Vtp|. Thus, |Vtp| ≤ VDD (3) Inequalities (2) and (3) are satisfied if: Max{|Vtp|, Vtn} ≤ VDD, and combining with (1), we get, Max{|Vtp|, Vtn} ≤ VDD ≤ |Vtp| + Vtn Problem 2 (5 points): A CMOS logic gate has a supply voltage of V volts and an output
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This note was uploaded on 09/17/2011 for the course ELEC 6970 taught by Professor Staff during the Spring '08 term at Auburn University.

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Test_6270_sol - ELEC 5270/ELEC 6270 Low-Power Design of...

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