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Unformatted text preview: Power Minimization using Voltage reduction and Parallel Processing Sudheer Vemula Dept. of Electrical and Computer Engineering Auburn University, Auburn, AL. Goal of the project:- To reduce the power consumed by the 32x32 array multiplier by including parallel processing, without any increase in the delay of the critical path. Problem Statement:- The array multiplier in itself has a lot of parallelism included, i.e, the processing is done simultaneously in most of the blocks. The initial intuition is that the further inclusion of parallelism in the same circuit may not have any further improvement. Design Approach:- Inclusion of parallelism should improve the speed of operation of the circuit. Then we can reduce the voltage supply, which will reduce the power dissipation but will increase the delay of the circuit. The additional delay added in the circuit should be compensated by the included parallelism and the circuit should be able to work at its normal frequency of operation. For including parallelism in the circuit additional circuitry might be added, which will increase the area overhead and also the power consumption. The amount of power dissipated may be high or low depending on the type of the overhead circuitry. The final power consumption of the circuit should be lower than the initial value by adding appropriate amount of overhead. Introduction:- Concurrent execution of several programs or several blocks of a program is known as parallel processing . There are two ways of including parallelism in the circuit. They are 1) Data Parallelism 2) Control Parallelism Data Parallelism is parallel execution of single expression on data distributed over multiple processors . Control Parallelism is the parallelism that is achieved by the simultaneous execution of multiple threads , i.e., performing different operations on same data simultaneously. Design Techniques:- There are two ways of including parallelism in the circuits. First, the same core can be replicated several times as shown in Fig.1. This is known as multi-core architecture. By replicating the same core several times the incoming inputs are applied to different cores in sequence. Now the individual cores can be slowed down by Voltage scaling which in turn will reduce the power consumption of the whole circuit. The area overhead is very high in multi-core architecture and this architecture will work for any circuit independent of the combinational logic present in the circuit....
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