Vemula_LowVolt_Parproc

Vemula_LowVolt_Parproc - Power Minimization Using Voltage...

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Nov. 29, 2005 ELEC6970-001 1 Power Minimization Using Voltage Reduction and Parallel Processing By Sudheer Vemula
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Nov. 29, 2005 ELEC6970-001 2 Outline:- Goal of the Project Introduction to Parallel Processing Delay of the critical path in the given circuit of 32x32 Array Multiplier Methods to introduce parallelism in the given circuit. Reduction in delay of critical path due to the introduced parallelism Calculations showing that the estimation of area and delay Conclusion
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Nov. 29, 2005 ELEC6970-001 3 Goal of the Project To reduce the power consumption of the circuit. By reducing the Voltage of the power supply. Consequence: Increases the delay of the critical path. To compensate the increase in delay by introducing parallelism. To calculate the reduction in power.
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Nov. 29, 2005 ELEC6970-001 4 Parallel Processing Definition:- Concurrent execution of several programs or several blocks of a program is known as parallel processing[1]. Types of parallelism Data Parallelism & Control Parallelism Data Parallelism is parallel execution of single expression on data distributed over multiple processors[2]. Control Parallelism is the parallelism that is achieved by the simultaneous execution of multiple threads [3].
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Nov. 29, 2005 ELEC6970-001 5 Voltage Scaling and Delay:- Since transistor is a voltage controlled current device, the resistance depends on the voltage and current. = 0.5(0.5 Rp C + 0.5 Rn C) RC 5 . 0 = τ ( 29 2 f r + = + = dsatp dsatn dd I I CV 1 1 4 ( 29 α t dd dd V V kV - = = 2 for low V dd
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Nov. 29, 2005 ELEC6970-001 6 Critical Path:- 0 0 0 0 0 0 0 0 A0 A1 A2 A3 B3 B2 B1 B0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 0 0 0 0 0 0 0 0 A0 A1 A2 A3 B3 B2 B1 B0 Y0 Y1 Y2 Y3
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Vemula_LowVolt_Parproc - Power Minimization Using Voltage...

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