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Unformatted text preview: ELEC 5770001/6770001 Fall 2010 VLSI Design Low Power VLSI Design
Vishwani D. Agrawal James J. Danaher Professor
Dept. of Electrical and Computer Engineering
Auburn University, Auburn, AL 36849
vagrawal@eng.auburn.edu
http://www.eng.auburn.edu/~
vagrawal/COURSE/E6770_Fall10/VLSID_Fall2010_LowPower.ppt Fall 2010, Nov 16
Fall ELEC5770001/6770001 Guest Lecture 1 Power Consumption of VLSI Chips Why is it a concern? Fall 2010, Nov 16
Fall ELEC5770001/6770001 Guest Lecture 2 ISSCC, Feb. 2001, Keynote
“Ten years from now,
microprocessors will run at
10GHz to 30GHz and be capable
of processing 1 trillion operations
per second – about the same
number of calculations that the
world's fastest supercomputer
can perform now.
Patrick P. Gelsinger
Senior Vice President
General Manager
Digital Enterprise Group
INTEL CORP. Fall 2010, Nov 16
Fall “Unfortunately, if nothing
changes these chips will produce
as much heat, for their
proportional size, as a nuclear
reactor. . . .”
ELEC5770001/6770001 Guest Lecture 3 VLSI Chip Power Density
Sun’s
Surface Power Density (W/cm2) 10000 Rocket
Nozzle 1000 100
8086 Nuclear
Reacto
r
Hot Plate 10 4004
8008 8085
386
286
8080
1
1970 Fall 2010, Nov 16
Fall 1980 P6
Pentium®
486
1990
Year Source: Intel® 2000 ELEC5770001/6770001 Guest Lecture 2010
4 LowPower Design
Design
Design practices that reduce power
consumption at least by one order of
magnitude; in practice 50% reduction
is often acceptable.
is
Lowpower design methods: Algorithms and architectures Highlevel and software techniques Gate and circuitlevel methods Test power
Fall 2010, Nov 16
Fall ELEC5770001/6770001 Guest Lecture 5 Specific Topics in LowPower Power dissipation in CMOS circuits
Transistorlevel methods Circuit and gate level methods Logic synthesis
Dynamic power reduction techniques
Leakage power reduction System level methods Lowpower CMOS technologies
Energy recovery methods
Ultra low power logic (subthreshold VDD) Microprocessors
Arithmetic circuits
Low power memory technology Test Power
Power estimation Fall 2010, Nov 16
Fall ELEC5770001/6770001 Guest Lecture 6 CMOS Logic (Inverter)
VDD No current flows
from power supply!
Where is power
consumed?
GND F. M. Wanlass and C. T. Sah, “Nanowatt Logic using FieldEffect MetalOxideSemiconductor Triodes,” IEEE International
SolidState Circuits Conference Digest, vol. IV, February 1963,
pp. 3233.
Fall 2010, Nov 16
Fall ELEC5770001/6770001 Guest Lecture 7 Components of Power Dynamic, Signal when output changes transitions (major component) Logic activity
Glitches Shortcircuit Static, (small) when signal is in steady state Leakage (used to be small) Ptotal =
=
Fall 2010, Nov 16
Fall Pdyn + P
Ptran + P + P ELEC5770001/6770001 Guest Lecture 8 Power of a Transition: Ptran
R = Ron V
i(t) vi (t)
Large
resistance v(t)
C Ground
C= Total load capacitance for gate; includes transistor capacitances
of driving gate + routing capacitance + transistor capacitances
of driven gates; obtained by layout analysis. Fall 2010, Nov 16
Fall ELEC5770001/6770001 Guest Lecture 9 Charging of a Capacitor
R
t=0 i(t) V v(t)
C Charge on capacitor, q(t) = C v (t) Current, i(t) = C dv(t)/dt Fall 2010, Nov 16
Fall = dq(t)/dt
ELEC5770001/6770001 Guest Lecture 10 i(t) = C dv(t)/dt =
dv(t)
∫ ───── =
V – v( t ) ln [V – v(t)] = [V – v(t)] /R
dt
∫ ────
RC
–t
── +
RC A Initial condition, t = 0, v(t) = 0 → A = ln V
v(t)
Fall 2010, Nov 16
Fall = –t
V [1 – exp(───)]
RC
ELEC5770001/6770001 Guest Lecture 11 v(t) = i(t) Fall 2010, Nov 16
Fall = –t
V [1 – exp( ── )]
RC dv(t)
C ───
dt = ELEC5770001/6770001 Guest Lecture V
–t
── exp( ── )
R
RC 12 Total Energy Per Charging
Transition from Power Supply Etrans =
= Fall 2010, Nov 16
Fall ∞
∫ V i(t) dt =
0 CV 2 ∞V
–t
∫ ── exp( ── ) dt
0R
RC 2 ELEC5770001/6770001 Guest Lecture 13 Energy Dissipated Per Transition in
Resistance
∞2
R ∫ i (t) d t 2 = 0 Fall 2010, Nov 16
Fall = V∞
– 2t
R ── ∫ exp( ── ) dt
R2 0
RC
1
2
─ CV
2 ELEC5770001/6770001 Guest Lecture 14 Energy Stored in Charged Capacitor
∞
∞
–t V
–t
∫ v(t) i(t) dt = ∫ V [1 – exp( ── )] ─ exp( ── ) dt
0
0
RC R
RC
1
2
= ─ CV
2 Fall 2010, Nov 16
Fall ELEC5770001/6770001 Guest Lecture 15 Transition Power Gate output rising transition
2 Energy
Energy dissipated in pMOS transistor = CV /2 Energy stored in capacitor = CV 2/2
Energy Gate output falling transition Energy
Energy dissipated in nMOS transistor = CV 2/2
2 Energy
Energy dissipated per transition = CV /2 Power dissipation:
2
Ptrans =
Etrans α fck =
α fck CV /2
α=
activity factor
fck = clock frequency
Fall 2010, Nov 16
Fall ELEC5770001/6770001 Guest Lecture 16 Components of Power Dynamic Signal transitions Logic activity
Glitches Shortcircuit Static Leakage Fall 2010, Nov 16
Fall Ptotal =
= Pdyn + P
P + Psc + P ELEC5770001/6770001 Guest Lecture 17 Short Circuit Power of a Transition: Psc
VDD
vi (t) i (t) CL
Ground Fall 2010, Nov 16
Fall ELEC5770001/6770001 Guest Lecture 18 ShortCircuit Power Increases with rise and fall times of input. Decreases for larger output load
Decreases
capacitance; large capacitor takes most of
the current.
the Small, about 510% of dynamic power
Small,
dissipated in charging and discharging of
the output capacitance.
the Becomes zero when VDD ≤ Vthn + Vthp
Becomes
Fall 2010, Nov 16
Fall ELEC5770001/6770001 Guest Lecture 19 Components of Power Dynamic Signal transitions Logic activity
Glitches Shortcircuit Static Leakage Fall 2010, Nov 16
Fall ELEC5770001/6770001 Guest Lecture 20 Static (Leakage) Power Leakage
Leakage power as a fraction of the total power
increases as clock frequency drops. Turning
supply off in unused parts can save power.
supply For a gate it is a small fraction of the total power;
For
it can be significant for very large circuits.
it Static power increases as feature size is scaled
Static
down; controlling leakage is an important aspect
of transistor design and semiconductor process
technology.
technology. Fall 2010, Nov 16
Fall ELEC5770001/6770001 Guest Lecture 21 CMOS Gate Power
R = Ron
vi (t) vi (t) V
i(t) v(t) Large
resistance C i(t) i (t) Ground
Leakage
current Fall 2010, Nov 16
Fall ELEC5770001/6770001 Guest Lecture time 22 Some Examples Fall 2010, Nov 16
Fall ELEC5770001/6770001 Guest Lecture 23 Energy Saving by Voltage Reduction
Battery
VDD = 0.9V, 500MHz
size
Efficiency
Battery lifetime
%
x103
seconds AHr Efficiency
% x10 11
cycles 1.2 93 1.263 7.03 3.6 VDD = 0.3V, 5MHz 103 4.198 22.80 Battery lifetime
x103
seconds 100+ x10 11
cycles 1234 48.60 seventimes
100+
3894 150.30 70 million gate circuit, 45nm CMOS bulk PTM.
Lithiumion battery.
Ref.: M. Kulkarni and V. D. Agrawal, “A Tutorial on Battery
Simulation – Matching Power Source to Electronic
System,” Proc. VLSI Design and Test Symp., July 2010.
Fall 2010, Nov 16 ELEC5770001/6770001 Guest Lecture 24 State Encoding for a Counter Twobit binary counter: State sequence, 00 → 01 → 10 → 11 → 00
Six bit transitions in four clock cycles
6/4 = 1.5 transitions per clock Twobit Graycode counter State sequence, 00 → 01 → 11 → 10 → 00
Four bit transitions in four clock cycles
4/4 = 1.0 transition per clock Graycode counter is more power efficient. G. K. Yeap, Practical Low Power Digital VLSI Design, Boston:
Kluwer Academic Publishers (now Springer), 1998.
Fall 2010, Nov 16
Fall ELEC5770001/6770001 Guest Lecture 25 Binary Counter: Original Encoding
Present
Present
state
state Next state a
A b a
0 b
0 A
0 B
1 0
1 1
0 1
1 0
1 1 1 0 0 A = ab + a b
B = ab + ab
Fall 2010, Nov 16
Fall B CK
CLR
ELEC5770001/6770001 Guest Lecture 26 Binary Counter: Gray Encoding
Present
Present
state
state Next state a
A a
0 b
0 A
0 B
1 0
1 1
0 1
0 1
0 1 1 1 0 A = ab + ab
B = a b + ab
Fall 2010, Nov 16
Fall B b CK
CLR
ELEC5770001/6770001 Guest Lecture 27 ThreeBit Counters
State Binary
No. of toggles Graycode
State
No. of toggles 000  000  001 1 001 1 010 2 011 1 011 1 010 1 100 3 110 1 101 1 111 1 110 2 101 1 111 1 100 1 000 3 000 1 Av. Transitions/clock = 1.75
Fall 2010, Nov 16
Fall Av. Transitions/clock = 1 ELEC5770001/6770001 Guest Lecture 28 NBit Counter: Toggles in Counting Cycle Binary counter: T(binary) = 2(2N – 1) Graycode counter: T(gray) = 2N T(gray)/T(binary) = 2N1/(2N – 1) → 0.5
Bits T(binary) T(gray) T(gray)/T(binary) 1 2 2 1.0 2 6 4 0.6667 3 14 8 0.5714 4 30 16 0.5333 5 62 32 0.5161 6 126 64 0.5079 ∞   0.5000 Fall 2010, Nov 16
Fall ELEC5770001/6770001 Guest Lecture 29 Transition
probability
based on
PI statistics FSM State Encoding
0.6
11 0.3 0.4
00
0.6 0.6 0.1 0.3 0.1
01 01
0.4 0.9 00
0.6 0.1 0.1
11 0.9 Expected number of statebit transitions: 2(0.3+0.4) + 1(0.1+0.1) = 1.6 1(0.3+0.4+0.1) + 2(0.1) = 1.0 State encoding can be selected using a powerbased cost function. Fall 2010, Nov 16
Fall ELEC5770001/6770001 Guest Lecture 30 FSM: ClockGating Moore
Moore machine: Outputs depend only on
the state variables.
the If
If a state has a selfloop in the state transition
graph (STG), then clock can be stopped
whenever a selfloop is to be executed.
whenever
Xi/Zk
Si
Sk
Sj Fall 2010, Nov 16
Fall Xj/Zk Xk/Zk
Clock can be stopped
when (Xk, Sk) combination
occurs. ELEC5770001/6770001 Guest Lecture 31 ClockGating in Moore FSM Flipflops PI Clock
activation
logic
CK
Fall 2010, Nov 16
Fall Latch Combinational
logic PO L. Benini and G. De Micheli,
Dynamic Power Management,
Boston: Springer, 1998.
ELEC5770001/6770001 Guest Lecture 32 Bus Encoding for Reduced Power Example: Four bit bus 0000 → 1110 has three transitions. If bits of second pattern are inverted, then 0000 →
If
0001 will have only one transition.
0001 Number of bit transitions
after inversion encoding Bitinversion Fall 2010, Nov 16
Fall encoding for Nbit bus: N N/2 0 0 N/2
Number of bit transitions
ELEC5770001/6770001 Guest Lecture N
33 Sent data Received data BusInversion Encoding Logic Polarity
decision
logic
Fall 2010, Nov 16
Fall Bus register
Polarity bit M. Stan and W. Burleson, “BusInvert Coding for Low Power I/O,”
IEEE Trans. VLSI Systems, vol. 3, no.
1, pp. 4958, March 1995. ELEC5770001/6770001 Guest Lecture 34 ClockGating in LowPower FlipFlop D D Q CK Fall 2010, Nov 16
Fall ELEC5770001/6770001 Guest Lecture 35 S5378 with GatedClock FF 2958 gates, 179 flipflops
TSMC025 CMOS
1,000 random vectors, clock period 50ns
Simulation by Powersim* Flipflops
used Normal Power (microwatts)
Combinational logic
Transitions Shortcircuit
14.1 0.13 Flipflops Total 220.3 751.6 1,081.5 Static
(leakage) 95.4 Clock Gated
133.5
23.1
0.13
118.9
32.5
308.0
* J. D. Alexander, “Simulation Based Power Estimation for Digital CMOS
Technologies,” Master’s Thesis, Auburn University, Dec. 2008.
Fall 2010, Nov 16 ELEC5770001/6770001 Guest Lecture 36 Books on LowPower Design (1) L. Benini and G. De Micheli, Dynamic Power Management Design Techniques and
L.
CAD Tools, Boston: Springer, 1998.
CAD
T. D. Burd and R. A. Brodersen, Energy Efficient Microprocessor Design, Boston:
T.
Energy
Boston:
Springer, 2002.
Springer,
A. Chandrakasan and R. Brodersen, LowPower Digital CMOS Design, Boston:
A.
LowPower
Boston:
Springer, 1995.
Springer,
A. Chandrakasan and R. Brodersen, LowPower CMOS Design, New York: IEEE
A.
LowPower
New
Press, 1998.
Press,
J.M. Chang and M. Pedram, Power Optimization and Synthesis at Behavioral and
J.M.
System Levels using Formal Methods, Boston: Springer, 1999.
System
M. S. Elrabaa, I. S. AbuKhater and M. I. Elmasry, Advanced LowPower Digital
M.
Circuit Techniques, Boston: Springer, 1997.
Circuit
R. Graybill and R. Melhem, Power Aware Computing, New York: Plenum
R.
Power
New
Publishers, 2002.
Publishers,
S. Iman and M. Pedram, Logic Synthesis for Low Power VLSI Designs, Boston:
S.
Logic
Boston:
Springer, 1998.
Springer,
J. B. Kuo and J.H. Lou, LowVoltage CMOS VLSI Circuits, New York: WileyJ.
LowVoltage
Interscience, 1999.
J. Monteiro and S. Devadas, ComputerAided Design Techniques for Low Power
J.
Sequential Logic Circuits, Boston: Springer, 1997.
Sequential
S. G. Narendra and A. Chandrakasan, Leakage in Nanometer CMOS
S.
Technologies, Boston: Springer, 2005.
Technologies
W. Nebel and J. Mermet, Low Power Design in Deep Submicron Electronics,
W.
Low
Boston: Springer, 1997.
Boston: Fall 2010, Nov 16
Fall ELEC5770001/6770001 Guest Lecture 37 Books on LowPower Design (2) N. Nicolici and B. M. AlHashimi, PowerConstrained Testing of VLSI Circuits,
N.
PowerConstrained
Boston: Springer, 2003.
Boston:
V. G. Oklobdzija, V. M. Stojanovic, D. M. Markovic and N. Nedovic, Digital System
V.
Clocking: High Performance and LowPower Aspects, WileyIEEE, 2005.
Clocking:
M. Pedram and J. M. Rabaey, Power Aware Design Methodologies, Boston:
M.
Power
Boston:
Springer, 2002.
Springer,
C. Piguet, LowPower Electronics Design, Boca Raton: Florida: CRC Press, 2005.
C.
LowPower
J. M. Rabaey and M. Pedram, Low Power Design Methodologies, Boston:
J.
Low
Boston:
Springer, 1996.
Springer,
S. Roudy, P. K. Wright and J. M. Rabaey, Energy Scavenging for Wireless Sensor
S.
Networks, Boston: Springer, 2003.
Networks
K. Roy and S. C. Prasad, LowPower CMOS VLSI Circuit Design, New York: WileyK.
LowPower
Interscience, 2000.
E. SánchezSinencio and A. G. Andreaou, LowVoltage/LowPower Integrated
E.
Circuits and Systems – LowVoltage MixedSignal Circuits, New York: IEEE
Circuits
New
Press, 1999.
Press,
W. A. Serdijn, LowVoltage LowPower Analog Integrated Circuits,
W.
LowVoltage
Boston:Springer, 1995.
Boston:Springer,
S. Sheng and R. W. Brodersen, LowPower Wireless Communications: A
S.
Wideband CDMA System Design, Boston: Springer, 1998.
Wideband
G. Verghese and J. M. Rabaey, LowEnergy FPGAs, Boston: springer, 2001.
G.
LowEnergy
G. K. Yeap, Practical Low Power Digital VLSI Design, Boston:Springer, 1998.
G.
Practical
K.S. Yeo and K. Roy, LowVoltage LowPower Subsystems, McGraw Hill, 2004.
K.S.
LowVoltage Fall 2010, Nov 16
Fall ELEC5770001/6770001 Guest Lecture 38 Books Useful in LowPower Design A. Chandrakasan, W. J. Bowhill and F. Fox, Design of HighA.
Design
Performance Microprocessor Circuits, New York: IEEE Press,
Performance
2001.
2001.
R. C. Jaeger and T. N. Blalock, Microelectronic Circuit Design,
R.
Third Edition, McGrawHill, 2006.
Third
S. M. Kang and Y. Leblebici, CMOS Digital Integrated Circuits,
S.
CMOS
New York: McGrawHill, 1996.
New
E. Larsson, Introduction to Advanced SystemonChip Test
E.
Design and Optimization, Springer, 2005.
Design
J. M. Rabaey, A. Chandrakasan and B. Nikolić, Digital Integrated
J.
Circuits, Second Edition, Upper Saddle River, New Jersey:
Circuits,
Upper
PrenticeHall, 2003.
PrenticeHall,
J. Segura and C. F. Hawkins, CMOS Electronics, How It Works,
J.
How It Fails, New York: IEEE Press, 2004.
How
N. H. E. Weste and D. Harris, CMOS VLSI Design, Third Edition,
N.
CMOS
Reading, Massachusetts: AddisonWesley, 2005.
Reading, Fall 2010, Nov 16
Fall ELEC5770001/6770001 Guest Lecture 39 Problem: Bus Encoding
A 1hot encoding is to be used for reducing the capacitive power consumption of an nbit data bus. All n bits are assumed to be independent and random. Derive a formula for the ratio of power consumptions on the encoded and the uncoded buses. Show that n ≥ 4 is essential for the 1hot encoding to be beneficial.
Reference: A. P. Chandrakasan and R. W. Brodersen, Low Power Digital CMOS Design, Boston: Kluwer Academic Publishers, 1995, pp. 224225. [Hint: You should be able to solve this problem without the help of the reference.] Fall 2010, Nov 16
Fall ELEC5770001/6770001 Guest Lecture 40 Solution: Bus Encoding
Uncoded bus: Two consecutive bits on a wire can be 00, 01, 10 and 11, each with a probability 0.25. Considering only the 01 transition, which draws energy from the supply, the probability of a data pattern consuming CV 2 energy on a wire is ¼. Therefore, the average per pattern energy for all n wires of the bus is CV 2n/4.
Encoded bus: Encoded bus contains 2n wires. The 1hot encoding ensures that whenever there is a change in the data pattern, exactly one wire will have a 01 transition, charging its capacitance and consuming CV 2 energy. There can be 2n possible data patterns and exactly one of these will match the previous pattern and consume no energy. Thus, the per pattern energy consumption of the bus is 0 with probability 2–n, and CV 2 with probability 1 – 2–n. The average per pattern energy for the 1hot encoded bus is CV 2(1 – 2–n). Fall 2010, Nov 16
Fall ELEC5770001/6770001 Guest Lecture 41 Solution: Bus Encoding (Cont.)
Power ratio =
Encoded bus power / uncoded bus power
=
4(1 – 2–n)/n → 4/n for large n
For the encoding to be beneficial, the above power ratio should be less than 1. That is, 4(1 – 2–n)/n ≤ 1, or 1 – 2–n ≤ n/4, or n/4 ≥ 1 (approximately) → n ≥ 4.
The following table shows 1hot encoded bus power ratio as a function of bus width:
n n 4(1 – 2–n)/n 1 2.0000 8 0.4981 2 1.5000 16 0.2500 = 1/4 3 1.1670 32 1/8 4
Fall 2010, Nov 16
Fall 4(1 – 2–n)/n 0.9375 64 1/16 ELEC5770001/6770001 Guest Lecture 42 ...
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