TABLE 123 - power supply of 2.5 V.----3)16-b, 32-Gb/s,...

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                                                                  TABLE 1: IMPLEMANTATION SUMMARY
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Parameters Software Platform Used/Hardware Platform Used Test Equipment Used Result Obtained Chances Of Improvement/Compromise Done Prototype Chip 1---On chip PRBS generators & BER analyser using 8-b data generator 2---BER Test conducted using -----1)on chip analyser -----2)agilent 863130A error performance analyser(BERT) 3----On-chip bord technicque 4-----High-speed signals were directly measured on- chip using high-impedance probes. On Chip High Impedence Port ---1)die microphotograh of the 2.1 *2 mm Prototype chip fabricated in 0.25- μ m CMOS technology ----2)
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Unformatted text preview: power supply of 2.5 V.----3)16-b, 32-Gb/s, 5-mm-long bus and an 8-b, 16-Gb/s, 10-mm-long bus, both using driver pre-emphasis, and a benchmark 16-b single ended VM static bus with similar bus routing area for comparison Of delay, power, and noise performance----4. Minimize the impact of wire bonding inductances B. Noise and Delay Performane 1)---Intrabus Crosstalk performance Single-ended signals at the receiver input were measured and converted to differential signal by the oscilloscope for an active victim pair and a quiet victim pair Oscillospe crosstalk between adjacent lines behaves primarily as common-mode noise 2)---noise swing differential aggressors quiet crosstalk is...
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This note was uploaded on 09/20/2011 for the course ELECTRONIC 102 taught by Professor Prof.s.c.badwaike during the Spring '11 term at University of Pune.

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TABLE 123 - power supply of 2.5 V.----3)16-b, 32-Gb/s,...

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