IngramGaryEE4352Homework4

IngramGaryEE4352Homework4 - and NMOS PMOS Problem 2:...

Info iconThis preview shows pages 1–2. Sign up to view the full content.

View Full Document Right Arrow Icon
Gary Ingram HW #4 EE 4352 Problem 1 Implement the equation using complementary CMOS. Size the devices so that the output resistance is the same as that of an inverter with an NMOS W / L = 2 and PMOS W / L = 6. Which input pattern(s) would give the worst and best equivalent pull-up or pull-down resistance? Using DeMorgan’s Theorem:
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Background image of page 2
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: and NMOS PMOS Problem 2: Implement the following expression in a full static CMOS logic fashion using no more than 10 transistors: Y = ( AB ) + ( ACE ) + ( DE ) + ( DCB ) Gary Ingram HW #4 EE 4352 Problem 3 Extract a transistor-level schematic for the following layout. What is the logic function?...
View Full Document

This note was uploaded on 09/21/2011 for the course EE 4352 taught by Professor Salamy during the Spring '11 term at Texas State.

Page1 / 2

IngramGaryEE4352Homework4 - and NMOS PMOS Problem 2:...

This preview shows document pages 1 - 2. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online