{[ promptMessage ]}

Bookmark it

{[ promptMessage ]}

IngramGaryEE4352Homework5

IngramGaryEE4352Homework5 - Gary lngram HW#5 EE 4352...

This preview shows pages 1–3. Sign up to view the full content.

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: Gary lngram HW #5 EE 4352 Problem 1 Either NAND gates or NOR gates can be used for implementing Boolean functions. Discuss which one of the two is more appropriate to be implemented in (i) complementary static CMOS logic, (ii) pseudo-NMOS logic. Explain in a few sentences. Show the transistor-based design of each gate in both cases. Static CMOS Pseudo NMOS 2m won V“ j> H. In static CMOS, the NAND is more logical to use, due to the setup of the PMOS transistors, because of delay, it is more ideal to have the PMOS transistors in parallel. In Pseudo NMOS, the pull up network is replaced by a transistor, this will make the NOR gate the better of the two for this particular configuration due to the pull down network being in parallel. Problem 2: V The figure below shows a two-input multiplexer. For this problem, assume independent, identically distributed uniform white noise inputs at A, S, and B. (3) Find the exact signal (P1) and transition (P0 9 1) formulas (values) for nodes X, Y, and Zfor: (1) a static, fully complementary CMOS implementation, and (2) a dynamic np-CMOS implementation. Assume only one transition during a clock cycle. Static Px(o—>1) = P =0Px=1 Pym—i1) = PY=0PY=1 sz—u) = Pz=on=1 PX=1 = PA=1PS=1 PY=1 = PB=1PS=1 Pz=o = PX=0PY=0 =1/2*1/2=1/4 =1/2“‘1/2=1/4 =3/4*3/4=9/16 PX=0=1_PX=1 PY=0=1_PY=1 Pz=1=1‘Pz=o =1‘1/4=3/4 =1‘1/4= /4 =1‘9/16=7/16 PX(0-)1)=1/ / PY(o—)1)=1/ * /. P2(o~1)=9/ .* / . Gary Ingram HW #5 EE 4352 Dynamic PX(0~—>1) = 1/4 Pym—.1) = 1/4 PZ(O—>1) = 3/4 (b) Compute the switching power consumed by the multiplexer. Assuming that all significant capacitances have been lumped into the three capacitors shown in the figure, where C: 0.3 pF. Assume that VDD = 2.5 V and independent, identically-distributed uniform white noise inputs, with events occurring at a frequency of 100 MHz. Perform this calculation on (1) a static, fully complementary CMOS implementation, and (2) a dynamic CMOS implementation. C = 0.3pF Vdd = 2.5V f= 100MHz Static fx(o—»1) = Px(o—>1) * fczock fy(o—>1) = P y(o—»1) * fclock f2(o—»1) = Pz(o—»1) * fczock = 3/16 * 100MHz = 3/16 * 100MHz = 63/256 * 100MHz = 18.75MHZ = 18.75MHZ = 24.61MHZ PX = CLVDD2f(O—>1) PY = CLVDDme—u) PX = CLVDDwa—n) = (0.3x10‘12)(2.5)2(18.75x105) = (0.3x1o-12)(2.5)2(18.75x106) = (0.3x10’12)(2.5)2(24.61x106) = 35.15mW = 35.15mW = 46.14HW Dynamic fx(o—>1) = Px(o—>1) * fClock fyw—u) = Pym->1) * fClock fz(o—>1) = Pz(o—»1) * fczock = 1/4 * 100MHz = 1/4 * 100MHz = 3/4 * 100MHz = 25MHZ = ZSMHZ = 75MHZ PX = CLVDDme—u) PY = CLVDDme-u) P2 = CLVDszw—bl) = (0.3x10-12)(2.5)2(25x106) = (0.3x10-12)(2.5)2(25x1o6) = (0.3x10'12) 2.5)2(75x106) = 46.87uW = 46.87uW = 14.06mW Gary Ingram HW #5 EE 4352 Problem 3 Design a robust full adder using transmission gates and static CMOS. A B S Cin '4 Vdd Com ...
View Full Document

{[ snackBarMessage ]}