EE 4352 - Exam 1 - Fall 2010

EE 4352 - Exam 1 - Fall 2010 - Texas State University The...

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Unformatted text preview: Texas State University The Ingram School of Engineering Electrical Engineering Program EE 4352: Introduction to VLSI Design Name: Queer: Br; 14:5: Test 1 Date: 10(0512910 18:00 am — 9:20 pm) Please Read the following instructions before you start. 1. This is a closed book closed notes test. 2. Equations are provided. 3. Solve all of the following fly; problems in any order you wish. 4 . Start solving the problems in the space allocated and use more paper sheets as needed. 5. Number your answer sheets properly. Dr. Hassan Salamy ‘ Page 1 Problem 1 a) Briefly answer the following questions. 1. What does CMOS stand for? 2. What is 3er loading? 3. What does NRE cost stand for? Give three examples. 4. Name three classes of parasitic in wires. ‘0) Draw a ring oscillator of 7 inverters. Assume that the propagation delay of each inverter is 10 ps. Find the frequency of the oscillation. c) In this problem, the circuit is implemented in 0.2511111 technology, and all the transistors have the minimum channel lengths. Consider the CMOS inverter in the Figure (a) below. If the NMOS transistor has charmel Width Wn and the PMOS transistor has channel width, Wp, label the voltage transfer characteristics from Figure (b) that correspond to following device sizes: A: W22: 5pm, Wp= 5pm B: Wn= 1pm, WP: 5pm C: WM: 511m, Wp= llfln Briefly explain your answers. C) Wt KM...) i—o gar seemed Fit—Saws in{’ Ms. W b... wach wM wk 39 b woulak broil-he. oxer gCuEh.I@ Marv)? We. WW “la is (lawman-r So on is fire. Ste-ER WH-M. Hue" lmgui— H. k “firmer—Coal NEWS. when w’“7 a)? m 25me Wnu\cL"‘r\m-M» a. \mcc) <25 Volt-«5L Ware-(x Show/K bY C. gf‘mQh. O )1 Dr. Hassan Salamy Page 2 [095 “L. CMOS ram-.9»; Gec comflmmhw mam omit 5m‘c ended—ec— 1‘ 5‘49 lawns is Mam ’me, Qantasmt, aluman in Y0“ {MOS d-W‘tt w a m bfb mosh fé) a44- O...5 cg. 3. owe, HM; flan-fadirdx-P C05 1. The, (.051- as WE’MY 2-605? as harem/elm? 3. (05?“ 06? mflcms «Mm Some, EXMWBS cal-L: bl , fefi'fi‘h-JLJ ENJUQ-tje.) CAEacQH-fL, TcX .v' — [Om ‘ 7 70¢S: W W Dr. Hassan Salamy Page 3 Problem 2: The figures below show the circuit diagram of a CMOS inverter and the VTC of an NMOS for different V03 values, respectively. a) What effect does VDS have on ID in resistive mode? b) What effect does V93 have on ID in saturation mode? 0) Draw the Corresponding VTC for a PMOS for the following v05 values: (-1.5 V, -1 V, w 0.5 V and 0 V) (1) Using the circuit diagram of the CMOS inverter above. Label the source, drain, and gate of the NMOS and PMOS. e) Using part (d) and any other analysis, prove the following equalities i. IDSp = 'IDSn ii. VGSE = Vin ; VGSp 3 Vin - Von iii- VDSn : Vout Q VDSp = Von: " VDD ‘ f) Use the equalities in parMe), Show the step by step transformation of the PMOS VTC in part (c) to a VTC with flnfi-the x—axis and IDrl as the y—axis. Assume VDD I 2.5 V. g) Redraw both of the NMOS VTC and the PMOS VTC on the same figure with W“ as the x—axis and ID,1 as the y-axis. I 17:31)}, - h) Draw the VTC of a CMOS inverter. i) Label the DC operating points on the VTC of the CMOS inverter with the mode of operation of the NMOS and the PMOS at each point. r 65‘) W Wyoa Cm Seal», «PM. {kywm 1195. Wrow Tm) in 0‘299srt'1 dz-cwumS. it) 0.3. [bf/V105 , 7 ‘j v “\1 = 11* «U .. h ,,, \J 5‘]; i at QMDS (43" 61" .5 “a DD UM'V5:‘}6:S' 'o MSW”) 5‘9 “a "‘ Dr. Hassan Salamy _ so Page 4 fl \fl I UbSCD ‘3- Vouk- U00 2. Qua ;“ $955ko male/- as 005 iAaeag’e’S ID also fflCA‘efiLSé-S dunk Ti- ?5 “haw (‘dod-IMSN‘E’ b} I“ SwJNWA-mm U95 hugs/x (‘0 8.9% on. 1030/05 Ms vary ohms-y- Jmfl ePP-uron 2b) Yes Q dusts—O ’ V 2'. as to U“ :" UL'IS‘ "1g 53 on REM“ . {WSW} W83 Dr. Hassan Salamy _ Page 5 Problem 3 The figure below shows NMOS and PMOS devices with drain, souICe, and gate ports annotated. Determine the mode of operation (saturation, resistive, or cutoff) and drain current 1;; for the biasing configuration given below. Use the following transistor data: NMOS: 16,; = llsuANZ, Vm : 0.43 v, t = 0.06 V], PMOS: k3, = 30 mm, Vm : —0.4 v, k = -0.1 v1. Assume (W/L) = 1 Configuration: NMOS: V05 = 0.6 V, V95- = 0.1 V. PMOSI VGS = “2.5 V, VDS = ~01 V. O! * v‘J '=~ .\7 3; eg’ hifiuafvr) " F] v r ' 37 ué‘s 1"" O n .158 Q" G v qu'urw 7 05 V 7Ur 10:1 Ise‘iflows] “‘57 o R S L‘ meant“ \/ vV-r 4' lies W S ‘11‘1 a m/ PMOS SodrvMNsA \t Ignore»; exigbflé/Nflf Dr. Hassan Salamy Page 6 Problem 4 Consider the circuit in the figure below. ‘ a) in order to‘drive a large capacitance (CL) from a minimum size gate (with input 3 capacitance CgJ), you decide to introduce a three—staged buffer as shown in the 6 W figure above. Assume that the propagation delay of the minimum size inverter is 8 Q0 ps. Also assume that the- input capacitance if a gate is proportional to its size. Determine the sizing of the three additional buffer stages that will minimize the propagation delay. Find this minimum propagation delay. '13) If you could add any number of stages to achieve the minimum delay, how many stages would you insert? What is the minimum propagation delay in this case assuming the propagation delay of the minimum size inverter is 8 ps? 0) Find the minimum propagation delay of a chain of 8 inverters assuming the propagation delay of the minimum size inverter is 8 ps. d) Find the total propagation delay of a chain of 4 inverters such that the gate _ capacitance of inverter (1' + I) is four times that of inverter (1'). Assume that the gate capacitance of the 4th inverter is 1%: CL Also assume that the prepagation delay of the . minimum size inverter is 8 ps. 09 ’2 2F: (“L/(,5: \ 7":1’Zg S-‘Lcs are. on alter q . :44 Gym: east“! {Waxth if? 2w Joe-.Lttteami?’ t? :1 lgg‘es Ida : b 159‘:— §ZSe$>01$3 : [USPS OkSSume, W;O ' 3/5, N: BEL eze gate) _ mm? lnLG) NI \ '” \noag) \H be:§,(9)(”~¢> 9:33qu :— 8995 @or‘s (,9er9363 Page 9 Dr. Hassan Salamy Problem 5 A- Answer the following three questions: 1- An NMOS has a drawn 1, of 1-4 pm and a drawn Wof 2.6 pm. During processing, active region is expanded all around by 0.12 pm and Polysiiicon is shrunk all around by 0.19 pm. a) Calculate L of the transistor that contributes to the current. b) Calculate W of the transistor that contributes to the current. 2— What is N-select? 3- Find the technology for a PL of 0.2 pm. B- it was shown in Chapter 4 that the resistance of a wire can be expressed as R = RJ L/W. 1- What is R0 in the equation above? 2- Consider below the top section of two square wires. Assume that the resistance of Wire 1 is 7.5 kg}. Find the resistance of Wire 2. Briefly explain your answer. W2 Wire I Wire2 " a.) New L: 1.4+ M—rnr L= ‘-7'N’W 15 13)wi w=1.{,+.\1 4217' welfllm i Q" N~Sq£G¢ Ts Hag, Vfigfm Whém you Me: Your}? 503%?» aux-k Macaw) in {—5937 a (3 , \* Q1 :3 “ML (#5:.Sf'qficer 99 lvum‘t— lusfix 09- i-‘AQ. Utre,O " ‘ 1 ,z L-‘L av. woe, 2L wnl We, a: 1.; q) 9 Dr. Hassan Saiamy Page 10 5") Cd? (‘02. d—fo n A A 619 L: l.L{—-0,l$L-—0.ri" .4/ “z, 4.01 ’%) w: gtgwgu— 0.11 m 21.55% ’1- Wml 7-5/“1t’ R073? W, R 75ML a0 a W Dr. Hassan Salamy ' Page 11 ...
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This note was uploaded on 09/21/2011 for the course EE 4352 taught by Professor Salamy during the Spring '11 term at Texas State.

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EE 4352 - Exam 1 - Fall 2010 - Texas State University The...

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