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Unformatted text preview: Texas State University
The Ingram School of Engineering
Electrical Engineering Program EE 4352: Introduction to VLSI Design Name: Queer: Br; 14:5: Test 1 Date: 10(0512910 18:00 am — 9:20 pm) Please Read the following instructions before you start. 1. This is a closed book closed notes test. 2. Equations are provided. 3. Solve all of the following ﬂy; problems in any order you wish.
4 . Start solving the problems in the space allocated and use more paper sheets as
needed. 5. Number your answer sheets properly. Dr. Hassan Salamy ‘ Page 1 Problem 1 a) Brieﬂy answer the following questions.
1. What does CMOS stand for?
2. What is 3er loading?
3. What does NRE cost stand for? Give three examples.
4. Name three classes of parasitic in wires. ‘0) Draw a ring oscillator of 7 inverters. Assume that the propagation delay of each inverter
is 10 ps. Find the frequency of the oscillation. c) In this problem, the circuit is implemented in 0.2511111 technology, and all the transistors
have the minimum channel lengths.
Consider the CMOS inverter in the Figure (a) below. If the NMOS transistor has charmel
Width Wn and the PMOS transistor has channel width, Wp, label the voltage transfer
characteristics from Figure (b) that correspond to following device sizes:
A: W22: 5pm, Wp= 5pm
B: Wn= 1pm, WP: 5pm
C: WM: 511m, Wp= llﬂn
Brieﬂy explain your answers. C) Wt KM...) i—o gar seemed Fit—Saws in{’ Ms. W b... wach wM wk
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Dr. Hassan Salamy Page 3 Problem 2: The ﬁgures below show the circuit diagram of a CMOS inverter and the VTC of an NMOS for
different V03 values, respectively. a) What effect does VDS have on ID in resistive mode?
b) What effect does V93 have on ID in saturation mode?
0) Draw the Corresponding VTC for a PMOS for the following v05 values: (1.5 V, 1 V,
w 0.5 V and 0 V)
(1) Using the circuit diagram of the CMOS inverter above. Label the source, drain, and gate
of the NMOS and PMOS.
e) Using part (d) and any other analysis, prove the following equalities
i. IDSp = 'IDSn
ii. VGSE = Vin ; VGSp 3 Vin  Von
iii VDSn : Vout Q VDSp = Von: " VDD ‘
f) Use the equalities in parMe), Show the step by step transformation of the PMOS VTC in
part (c) to a VTC with ﬂnﬁthe x—axis and IDrl as the y—axis. Assume VDD I 2.5 V.
g) Redraw both of the NMOS VTC and the PMOS VTC on the same ﬁgure with W“ as the
x—axis and ID,1 as the yaxis. I 17:31)},
 h) Draw the VTC of a CMOS inverter.
i) Label the DC operating points on the VTC of the CMOS inverter with the mode of
operation of the NMOS and the PMOS at each point. r 65‘) W Wyoa Cm Seal», «PM. {kywm 1195. Wrow
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53 on REM“ . {WSW} W83 Dr. Hassan Salamy _ Page 5 Problem 3 The ﬁgure below shows NMOS and PMOS devices with drain, souICe, and gate ports annotated.
Determine the mode of operation (saturation, resistive, or cutoff) and drain current 1;; for the
biasing conﬁguration given below. Use the following transistor data: NMOS: 16,; = llsuANZ,
Vm : 0.43 v, t = 0.06 V], PMOS: k3, = 30 mm, Vm : —0.4 v, k = 0.1 v1. Assume (W/L) =
1 Conﬁguration: NMOS: V05 = 0.6 V, V95 = 0.1 V.
PMOSI VGS = “2.5 V, VDS = ~01 V. O! * v‘J '=~ .\7
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exigbﬂé/Nﬂf Dr. Hassan Salamy Page 6 Problem 4 Consider the circuit in the ﬁgure below. ‘ a) in order to‘drive a large capacitance (CL) from a minimum size gate (with input 3 capacitance CgJ), you decide to introduce a three—staged buffer as shown in the
6 W ﬁgure above. Assume that the propagation delay of the minimum size inverter is 8
Q0 ps. Also assume that the input capacitance if a gate is proportional to its size. Determine the sizing of the three additional buffer stages that will minimize the
propagation delay. Find this minimum propagation delay. '13) If you could add any number of stages to achieve the minimum delay, how many
stages would you insert? What is the minimum propagation delay in this case
assuming the propagation delay of the minimum size inverter is 8 ps? 0) Find the minimum propagation delay of a chain of 8 inverters assuming the
propagation delay of the minimum size inverter is 8 ps. d) Find the total propagation delay of a chain of 4 inverters such that the gate
_ capacitance of inverter (1' + I) is four times that of inverter (1'). Assume that the gate
capacitance of the 4th inverter is 1%: CL Also assume that the prepagation delay of the . minimum size inverter is 8 ps.
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lnLG) NI \ '” \noag) \H be:§,(9)(”~¢> 9:33qu :— 8995 @or‘s (,9er9363 Page 9 Dr. Hassan Salamy Problem 5 A Answer the following three questions: 1 An NMOS has a drawn 1, of 14 pm and a drawn Wof 2.6 pm. During processing,
active region is expanded all around by 0.12 pm and Polysiiicon is shrunk all
around by 0.19 pm. a) Calculate L of the transistor that contributes to the current.
b) Calculate W of the transistor that contributes to the current.
2— What is Nselect?
3 Find the technology for a PL of 0.2 pm. B it was shown in Chapter 4 that the resistance of a wire can be expressed as R = RJ L/W.
1 What is R0 in the equation above?
2 Consider below the top section of two square wires. Assume that the resistance
of Wire 1 is 7.5 kg}. Find the resistance of Wire 2. Brieﬂy explain your answer.
W2 Wire I Wire2 " a.) New L: 1.4+ M—rnr L= ‘7'N’W 15
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Dr. Hassan Salamy ' Page 11 ...
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This note was uploaded on 09/21/2011 for the course EE 4352 taught by Professor Salamy during the Spring '11 term at Texas State.
 Spring '11
 Salamy

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